Feature: System Design
System Phase Calibration The CONVST pin manages the start of a conversion such that it triggers the process simultaneously on all channels. However, on applications where currents are measured through current transformers (CTs) while voltages are scaled down through a voltage divider, there will be a phase mismatch between current and voltage channels. To compensate for that, AD7606B can delay the sampling instant on any channels, such that the output signals can be realigned in phase, as shown in Figure 5.
Figure 3. Offset error when the sensor gets disconnected from the ADC’s analogue inputs
System Robustness In order to increase system reliability, several diagnostic features have been included on-chip, namely: • Overvoltage/undervoltage comparators on every channel.
• An interface check that clocks out fixed data on each channel in order to verify the communication.
• SPI invalid read/write alerts if there is an attempt to write to or read from an invalid register.
• BUSY STUCK HIGH alerts if the BUSY line continues longer than the normal time after a conversion has been initiated.
• Reset detection alerts if a reset has been detected for either a full, partial, or power-on reset on the internal LDO regulator.
Figure 4. Sensor disconnect detection
• CRC can be performed in the memory map, ROM, and every interface communication in order to guarantee correct initialisation and/ or operation.
Conclusion The AD7606B brings a complete data acquisition system on a chip to the market. All the analogue front-end building blocks are implemented. It provides a complete set of advanced diagnostic features, as well as gain, offset, and phase-calibration. With this, the AD7606B reduces component cost and system design complexity, easing the journey to designing power line monitoring applications.
Figure 5. Phase realignment 24 November 2024
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