Column: JESD204 standard
then it’s time to turn on both. As for how much gain to set each of them to, one advantage of specifying response in terms of insertion loss (and gain) is that it’s additive. For example, at the frequency of interest, a PCB trace with -20dB of loss, a transmitter with +6dB of pre-emphasis, and a receiver with +8dB of equalisation can be represented as -20dB + 6dB + 8dB = -6dB total.
Noise and jitter No end system design is free of noise and jitter. Emulating system jitter is fully specified in the JESD204B specification, but voltage noise is not. To emulate voltage noise in end system designs, component manufacturers can perform noise tolerance tests. One such test is power-supply noise tolerance. For this test, noise is injected onto the components’ various power-supply domains. The amplitude of the noise is increased until the first compliance test fails (often the first test to fail on a SerDes will be jitter). This test is repeated over the frequency range at which PCB noise is typically present (a few Hz to around 100MHz). A plot of maximum power supply noise tolerated vs. frequency is generated. The same test can be performed on all other pins. The end result of all this testing is typically a set of practical PCB design
recommendations, such as “keep a particular supply domain separated”, “use a bypass capacitor on this pin” or “don’t route any signals near this pin”.
Signal integrity As with any high-speed serial test application, a number of best practices apply to ensure accurate measurement results, and you must be sure that your instrumentation offers sufficient performance and signal integrity to deliver accurate measurement results. The following are a few considerations: • Dynamic range: in general, it is best to use your oscilloscope’s full analogue- to-digital dynamic range without clipping the amplifier. Although clipping might be acceptable when looking at a clock signal, doing this will hide ISI issues when evaluating data signals and can also affect the instrument’s edge-interpolation algorithm.
• Sample rate: setting the oscilloscope to its highest sample rate provides the best timing resolution for the most accurate signal and jitter measurement. One exception would be if you are looking over longer time window at lower timing accuracy.
• Capture window: analysing signals over a longer time-window allows you to see low-frequency modulation
effects like power supply coupling and spread-spectrum clocking. Increasing the capture window unfortunately increases the analysis processing time. On SerDes systems, there is often no need to look at modulation effects below the loop bandwidth of the CDR that are tracked and rejected.
• Test-point access and de-embedding: ensure that you employ a mechanism for keeping the probe as close to the transmitter and receiver test- points as possible. High-speed signalling test, timing and amplitude measurements can seriously impact margin-test results if the measurement process introduces unwanted signal discontinuity from long traces and/or fixturing from the actual transmitter/ receiver test points. In some cases, the probe access point
could be at a location where the signal is degraded due to transmission line length. In this case, you might have to de-embed the transmission line to see what the real signal is. De-embedding involves recreating a model (using a linear method with S parameters) of the measurement channel between the instrument and the targeted test-point. This model can be applied to acquired waveform data in the oscilloscope to account for those transmission line degradations; Figure 4.
Figure 4: Eye diagrams illustrating measurements taken at test fixture, end of channel and post-EQ
www.electronicsworld.co.uk November 2021 17
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