Column: JESD204 standard
is that correct? How many multiframes does the ILAS last? Is the ILAS the same on all lanes? Clearly, there is a lot of potential for protocol testing around the ILAS sequence. JESD204B does not have a lot of
handshaking, but what it does have can be tested. Depending on the subclass, a number of tests can be performed. Since the SYNC~ signal can be used for initial handshaking, error reporting and link re-initialisation, do the transmitter and receiver components do their part accordingly? Does the receiver assert SYNC~ starting at the right time and for the right duration? Does the transceiver react correctly based on the duration of SYNC~ assertion? Since the data sent over the link also plays a part in the handshaking (that is, the ILAS), is it correct for its content and with respect to SYNC~ timing? Next, there are a number of smaller
digital functions that need to be tested as part of the protocol, including scrambling, 8B/10B encoding/decoding, skew and skew tolerance, control bits, tail bits, SYNC~ signal combining, frame alignment monitoring, and correction. All these functions need to be validated. Lastly, there is the category of
protocol tests called “error handling”. The specification includes a minimum set of errors that must be detected and reported: disparity errors, not-in-table errors, unexpected control character errors, and code group synchronisation
There are a number of smaller digital functions that need to be tested as part of the
protocol, including scrambling, 8B/10B encoding/decoding, skew and skew tolerance, control bits, and more
errors. But there are many more potential errors that could be detected and reported. For each and every type detectable by a JESD204B component, there should be a protocol test. These protocol tests can be a bit of a challenge to perform and validate, because a properly working link will never exercise them – they generally require specialised test equipment. A bit error rate test (BERT) pattern generator can be used for many tests by creating a pattern that includes an error. Error cases can also be generated using an FPGA with code modified to specifically generate those errors.
Pre-emphasis and equalisation testing The JESD204B specification talks very little about pre-emphasis and equalisation. There are a few comments like “pre-emphasis might be required” and “equalisation might need to be implemented” from which one can infer that the specification allows them but does not give any additional guidance. When using a converter with JESD204B that includes pre-emphasis or equalisation, how does one go about determining whether or not to turn it on, and, if so, how by how much? To answer that question it is first best
to understand the type of jitter called intersymbol interference (ISI). ISI is the name for the variation in edge timing
Figure 2: Eye diagram at the end of a long ISI PCB
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