Column: Silicon systems design


Figure 1: Simulation samples partial state space; formal verifi cation reasons over full reachable states


architecture introduces machine, supervisor and user modes, CSRs, traps, memory protection and optional hypervisor support. T e result is not a


single-processor defi nition but a wide space of valid implementations within a shared architectural framework. Figure 2 shows how complexity grows by


composition. Each additional architectural dimension introduces new legal states and new interactions. CSR legality, privilege isolation, memory protection and extension


Figure 2: Composition of the RISC-V ISA


www.electronicsworld.co.uk May 2026 13


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