Feature: Embedded design
most important benefits from moving the algorithm’s execution from an MCU to an FPGA become apparent – as a reference, this step is equivalent to the ‘system management through a microcontroller’ setup, described earlier. Modern FPGA tools allow for a suite of optimisations and enhancements that greatly enhance the performance of complex algorithms. Before analysing the results, there are
some important terms to bear in mind: • Latency – The number of clock cycles required to execute all iterations of the loop;
• Interval – The number of clock cycles before the next iteration of a loop begins to process data;
• Block random access memory (BRAM); • DSP48E – Digital signal processing slice for the UltraScale architecture;
• Flipflop (FF); • Look-up table (LUT); • Unified Random-Access Memory (URAM) – which can be a single transistor.
Default Te default optimisation setting comes from the unaltered result of translating the C-based algorithm to synthesisable HDL. No optimisations are enabled, and this can be used as a performance reference to better understand the other optimisations.
Pipeline Inner Loop Te PIPELINE directive instructs Vivado HLS to unroll the inner loops so that new data can start being processed with earlier data still in the pipeline. Tus, new data does not have to wait for the existing data to complete before its processing begins.
Pipeline Outer Loop Applying the PIPELINE directive to the outer loop makes it pipelined. However, the inner loops’ operations now occur concurrently. Both the latency and interval time are cut in half through applying this directly to the outer loop.
Array Partition This directive maps the contents of the loops to the arrays and thus flattens all of the memory access to single elements within them. Hence, more RAM is consumed, but again, the execution time of this algorithm is halved.
Dataflow This directive allows the designer to specify a target number of clock cycles between each input read. This directive is only supported for top-level functions. Only loops and functions exposed to this level will benefit from this directive.
Inline The INLINE directive flattens all loops, both inner and outer, so that both row and column processes can execute concurrently. The number of required clock cycles is minimised, even if this consumes more FPGA resources.
Table 1: FPGA algorithm execution optimisation findings – latency and interval
Table 2: FPGA algorithm execution optimisation findings – resource utilisation
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