Feature: Embedded design
Figure 8: Xilinx Vivado HLS design flow
can be added flexibility and is future- proofed. Even within existing systems, the co-processor architecture provides design options, which would otherwise not be available.
The advantage of rapid prototyping Rapid prototyping executes tasks in parallel, and quickly identifies bugs and design problems. It also validates data and signal paths, especially those within a project’s critical path. However, for this process to truly produce streamlined, efficient results it should be coupled with sufficient, relevant expertise of hardware, embedded soſtware, DSP, or HDL engineers. Although nowadays there are plenty of interdisciplinary professionals who can tackle one or more of these tasks, there will still be substantial project overhead when it comes to coordinating those efforts. Te authors of the paper “An FPGA-
Based Rapid Prototyping Platform for Wavelet Co-processors” state that the co-processor architecture allows a single DSP engineer to fulfill all these roles, efficiently and effectively. For its study, the team designed and simulated a DSP functionality within the MATLAB Simulink tool, to: (1) verify the performance through simulation; and (2) act as a reference for future designs. Post-simulation, critical functionalities
were identified and divided into different cores – these are soſt-core components and processors that can be synthesised
22 May 2022
www.electronicsworld.co.uk
Empirical findings not only confirm the flexibility of the co-processor architecture, but also highlight the performance- enhancing options attained through modern FPGA tools
within an FPGA. Te most important step here was to define the interface among these cores and components, and to compare the data-exchange performance against the desired, simulated performance. Tis design process closely aligned with Xilinx’s design flow for embedded systems; see Figure 7. By dividing the system into
synthesisable cores, the DSP engineer can focus on the most critical aspects of the signal processing chain, without needing hardware or HDL expertise to modify, route or implement different soft-core processors or components within the FPGA. With an awareness of the data formats and interfaces, the engineer has full control over the signal paths and system-performance refinement.
Discrete cosine transform case study Empirical findings not only confirm the flexibility of co-processor architecture, but also highlight the performance-enhancing options attained through modern FPGA tools. In this example, a discrete cosine
transform (DCT) was selected as a computationally-intensive algorithm, used in digital-signal processing for pattern recognition and filtering. Te progression of the algorithm from a C-based implementation to an HDL-based implementation was at the heart of the findings, using the Vivado HLS v2019 tools. Beginning with the C-based
implementation, the DCT algorithm accepts two arrays of 16-bit numbers: array A is the input array to the DCT, and array B is the output array from the DCT. Te data width (DW) is therefore defined as 16, and the number of elements within the arrays (N) is 1024/DW, or 64. Te size of the DCT matrix (DCT_SIZE) is set to 8, which defines it as an 8 x 8 matrix. Although an important consideration,
the validation process values functionality over execution time, which is allowed, since the ultimate implementation of this algorithm will be in an FPGA, where hardware acceleration, loop unrolling and other techniques are readily available. Once the DCT code was created
within the Vivado HLS tool, the next step was to synthesise the design for FPGA implementation. At this step some of the
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