Feature: Embedded design
integrated into the design, which is not possible with some architectures, such as a single-chip, system-on-a-chip (SoC) architecture, or a high-performance DSP or MCU that can handle all the product’s processing. Te co-processor approach is a good mix of capability and flexibility, giving the designer more choices and freedom in the development stages and aſter its release to the market.
Figure 4: Application program, host processor and FPGA-based hardware used in a satellite communications setup
Satellite communications example Simply put, the value of a co-processor is to offload the primary processing unit so that tasks are executed in hardware, in which accelerations and streamlining can be maximised. Te advantage here is increased computational speed and performance, yet with a reduction in development time and cost – compelling arguments for space communications systems. In the “FPGA-Based Hardware as
Coprocessor”, authors G. Prasad and N. Vasantha explain how data processing within an FPGA serves the computational needs of satellite communications systems without the high non-recurring engineering (NRE) costs of application- specific integrated circuits (ASICs) or the application-specific limitations of a hard- wired processor architecture. As described earlier, their design begins
Figure 5: Infotainment FPGA co-processor architecture, example 1
Product release Both the MCU and FPGA are field- updateable devices. Several advancements have made FPGA updates just as accessible as soſtware updates. Moreover, since the FPGA is within the MCU’s addressable memory space, the MCU can serve as the access point for the entire system, receiving updates for both processors, which can be conditionally scheduled, distributed or customised by the user. Last of all, since user and use-case logs
record build implementations, system performance can be refined and enhanced, even aſter the product is in the field. Tis total-system updateability is most
20 May 2022
www.electronicsworld.co.uk
pronounced in space-based applications, where system maintenance and updates are performed remotely – from changing logical conditions to complicated updates of the comms modulation schemes. Te programmability offered by the FPGA and co-processor architecture can accommodate an entire range of capabilities. Tis hardware setup can also bring
system cost reductions. For example, it may be discovered during field deployments that the product can operate just as well with a cheaper MCU or lower-performance FPGA. Furthermore, should a component become unavailable or obsolete, new components can be
with the application processor performing the majority of computationally- intensive algorithms. From this starting point, they identify the key sections of soſtware that consume most of the CPU’s clock cycles, and migrate these over to HDL implementation. Te graphical representation is very similar to what has been presented so far; however, they have chosen to represent the application program as an independent block, to be realised either in the host (processor) or the FPGA-based hardware. Peripherals’ performance is
dramatically increased by using a peripheral component interconnect (PCI) interface and the host processor’s direct memory access (DMA). Tis was most obvious in the de-randomisation process, performed by the host processor’s soſtware. Tere was a bottleneck in the
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