Feature: Embedded design
Maximising the benefits from two technologies in the co-processor architecture By Noah Madinger, Senior Engineer, Colorado Electronic Product Design
D
eveloping electronic designs is fraught with challenges – from system performance expectations to schedule and budgetary limits. A
design approach that will help juggle these successfully begins with the hardware. A hardware architecture that combines
microcontrollers (MCUs) with field- programmable gate arrays (FPGAs) is known as a “co-processor architecture”, and with the strengths of both processor technologies it enables the embedded designer to meet demanding requirements, with the added flexibility to address other challenges, too. Te co-processor architecture combines the development speed and performance of an MCU with the flexibility of an FPGA. With further optimisations and performance enhancements offered at every step, the co- processor architecture can meet the most challenging requirements – both for today’s and future designs.
18 May 2022
www.electronicsworld.co.uk
Strengths One common application for FPGA designs is to interface directly with a high-speed analogue-to-digital converter (ADC). Te signal is digitised, read into the FPGA, DSP algorithms applied to it, upon which the FPGA makes a decision what to do with it next. Figure 1 shows a generic co-processor
architecture, where the MCU connects to the FPGA through an external memory interface; i.e, the FPGA is treated as if it were external static random-access memory (SRAM). Te FPGA feeds signals to the MCU, which serves as hardware interrupt lines and status indicators, allowing the FPGA to indicate critical states to the MCU, such as, for example, alerting it that an ADC conversion is ready, there’s a fault, or something else.
DSP and MCU In the first development stage, the MCU is at the centre of the DSP and MCU architecture; see Figure 2. All things being
equal, MCU- and executable-soſtware development is less resource- and time- consuming than the development with FPGAs and the hardware descriptive language (HDL). Tus, by initiating product development with the MCU as primary processor, algorithms can quickly be implemented, tested and validated. Tis also allows algorithmic and logical bugs to be discovered early on, with the opportunity to test and validate substantial portions of the signal chain. Here, the FPGA’s role is to serve as
a high-speed data-gathering interface. Its task is to reliably pipe data from the high-speed ADC, alert the MCU to that data and present it to its external memory interface. Although this role does not include implementing HDL-based DSP processes or other algorithms, it is nonetheless highly critical. Te FPGA development performed in this phase lays the foundation for the product’s ultimate success, both during product development and aſter its market release. By focusing
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