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supply and data communication lines are subject to the same EMC disturbance, adding additional complexity when designing for EMC. EMC filtering components need to be carefully chosen to mitigate against power supply disturbances, but also must not reduce the data circuit communication bandwidth.
System-level EMC standards, such as IEC 61000-4-6 conducted RF immunity, are specified for many industrial products, with manufacturers stating product immunity to Class A (no communication errors) or Class B (communication errors, but the system does not need to be reset).
The threshold for Class A compliance can vary from manufacturer to manufacturer and is usually identified by a bit error rate (BER), or equivalent microvolt or micro-g range for vibration sensors. The Class A compliance threshold is typically a very low voltage, much lower than the minimum signal that the system can measure. The conducted RF immunity standard allows the user to define pass/fail criteria for the system using a BER, while specifying some setup details and noise injection levels. There is plenty of scope for interpretation in regards to what is the most appropriate setup and BER, and this poses a challenge for the system designer: how to match the lab design verification test setup to the real customer application, particularly when small changes in test setup can yield dramatic changes in test results.
Most common EMC test procedures need the full system to be built before going to the EMC certification lab to test it. Full systems include cable choice, length, and shielding. Different cables have different capacitance specifications, which in turn can couple more or less EMC noise into the affected system. Cable length and shield grounding can lead to impedance mismatches at high EMC frequencies as well as different ground current return paths. When a system is built, the preferred test method is that each sub-unit be individually tested for EMC immunity; however, in the real application the entire system will be subjected to the same EMC noise. These are just some of the reasons why it is difficult to correlate factory EMC testing with customer lab tests. Given today’s highly-integrated designs and EMC test complexity, it is clear that a time- efficient, flexible approach to design for EMC is needed. Simulation before and during lab testing is the answer. Getting the right lab results, with minimum time and effort invested, is the goal.
Using Virtual Lab to Accelerate Debug and Solve EMC Issues Analog Devices’ system-level expertise and EMC simulation techniques have resulted in the development of a virtual lab simulation flow, as described in Figure 2. A virtual lab environment makes it easier to get design for EMC right the first time, with virtual design iterations performed instead of time-consuming and costly lab setup and measurement iterations. Computing power, SPICE, electromagnetic field simulators and CAD software have converged and reached a maturity point where this virtual lab is feasible, where engineers can now achieve unprecedented levels of accuracy and simulation speed. PCBs, cables, integrated circuit chips and passive components can be modeled, as well as EMC stimulus. The results can be analysed, with rapid identification of circuit weaknesses and targeted recommendations for improvement. Using the virtual lab environment, the designer can access any physical node of the system during the tests without the typical measurement limitations found at the real lab – for example, measurement equipment bandwidth, lab limitations, non-ideal impedances of the probes, and external noise – interfering with the measurements.
Several common industrial IEC 61000 system- level EMC standards tests can be simulated prior to PCB fabrication; see the full list of requirements at
https://www.analog.com/en/ technical-articles/achieving-99-percent-improve-
in-emc-compliance-for-mems-sys.html.
MEMS and Simulation Case Study This section describes a simulation case study and correlation with lab measurements, using the Figure 3 vibration monitoring circuit with Analog Devices’ ADXL1002 MEMS accelerometer. The
circuit contains two shunt regulators, one of which (IC1) powers the accelerometer and the AD8541 op-amp (IC3), and a second (IC4) that provides a 9.5Vdc bias. When the system is powered and the ADXL1002 is static, the communication bus rests at 12Vdc. The circuit in Figure 2 requires compliance to IEC 61000-4-6 conducted RF immunity, which is a common requirement for equipment operating in industrial applications.
Correlating real lab and virtual lab simulation requires several process steps, summarised as follows: 1. Real lab setup and simulation environment correlation;
2. Develop simulation models using virtual lab (Figure 2);
3. Use simulation to identify design for EMC weaknesses;
4. Use simulation to identify design for EMC improvements;
5. Validate design for EMC improvements in the real lab.
Step 1: Real Lab Setup and Simulation Environment Correlation The IEC 61000-4-6 conducted RF immunity test is applicable to products that operate in environments where radio frequency (RF) fields are present. The RF fields can act on the entire length of cables connected to installed equipment. In the IEC 61000-4-6 test, an RF voltage is stepped from 150kHz to 80MHz. The RF voltage is 80% amplitude modulated (AM) by a 1kHz sinusoidal wave. The IEC 61000-4-6 standard specifies Level 3 as the highest RF voltage at 10V/m. The RF voltage is injected to the cable shield, or capacitively coupled using a clamp. As shown in Table 1, several key parameters need to be correlated between the virtual and real lab environment:
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Figure 2: Moving from real lab to virtual lab environment
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