Feature: Processors and MCUs


Removing MCU Flash has profound consequences


for processor architecture, booting, security, firmware updates and, perhaps most noticeably for developers, software complexity


longer contain large amounts of on-chip Flash. Application code is instead held in external serial memory and either executed directly from it or copied into large banks of internal SRAM. Devices such as Infineon’s PSOC Edge and STMicroelectronics’s STM32N6 illustrate this trend particularly well. This is not simply a change in memory technology.


Flashless MCU and its implications for modern- day embedded system design


By Trevor Martin, Technical Specialist, NDEmbedded


F


or decades, the architecture of a high- performance microcontroller was reassuringly familiar. A processor core sat alongside SRAM, embedded Flash and a collection of peripherals, all on the same piece of silicon. Power up the device, and the processor fetched its reset vector


directly from internal Flash and execution of the application code began. Developing an application typically involved compiling and debugging a single project. That model is now changing. A new generation of high- performance microcontrollers is appearing, which no


20 October 2026 www.electronicsworld.co.uk


Removing MCU Flash has profound consequences for processor architecture, booting, security, firmware updates and, perhaps most noticeably for developers, software complexity.


Why lose the Flash? The principal motivation for losing the Flash is semiconductor process technology. Embedded Flash has historically been extremely convenient for microcontrollers, but it becomes increasingly difficult and expensive to integrate as semiconductor geometries shrink. Logic transistors scale relatively well to advanced process nodes; conventional embedded Flash does not. Therefore, at some point, the Flash process will become a limiting factor when choosing the fabrication technology for an otherwise high-performance MCU. Removing internal Flash gives semiconductor vendors access to higher gate counts, higher clock rates and lower power technologies. Some manufacturers are adopting emerging non-volatile


technologies like resistive RAM (RRAM) to retain modest quantities of on-chip non-volatile storage. RRAM is attractive at smaller geometries, but remains relatively expensive in area and process complexity, so it makes sense to reserve it for boot code, security configuration and other relatively small, trusted components rather than tens of megabytes of application storage. Infineon’s advanced MCU, PSOC Edge, is a good example


of this approach. The family combines RRAM with up to 6MB of on-chip SRAM. Its RRAM participates in a multi-stage boot architecture, while the much larger SRAM provides the working memory demanded by sophisticated edge applications. Infineon’s E84 devices combine this memory architecture with a Secure Enclave (a dedicated, hardware- isolated secure subsystem integrated into a device’s main


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