Column: Silicon systems design
Building trustworthy AI workfl ows for semiconductor engineering
state spaces. Static analysis identifi es structural risks. Regression systems schedule jobs and aggregate results. Coverage tools measure what has been exercised.
Agentic AI adds another layer. It can By Mike Bartley, CEO, Alpinum
T e critical question is no longer only what an agent can do, but how its decisions can be independently checked and converted into defensible engineering evidence. AI agents are moving beyond isolated
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assistance in semiconductor engineering. Instead of responding to a single prompt, an agent can interpret an objective, plan a sequence of actions, call engineering tools, inspect the results and decide what to do next. Recent EDA announcements from Siemens, Cadence and Synopsys show that long-running and increasingly autonomous workfl ows are moving rapidly towards practical design and verifi cation use.
I agents are beginning to execute longer semiconductor engineering workfl ows without continuous human intervention.
T at changes the question facing
verifi cation teams. T e issue is no longer only whether AI can generate useful tests, assertions or debug suggestions; but, if an autonomous workfl ow can establish enough trustworthy evidence to justify its next action. T is is where the phrase “self-
verifying AI” needs careful engineering interpretation. An agent reviewing its own reasoning is not the same as independent verifi cation. Confi dence comes when AI-generated actions are checked against controlled requirements, trusted engineering tools, reproducible results and explicit acceptance criteria.
The verifi cation problem moves up a level Traditional verifi cation already contains extensive automation. Simulation executes tests automatically. Formal engines explore
decide which tools to invoke, in what order, and based on which intermediate result. For example, an agent investigating an uncovered power-management transition might retrieve the relevant requirement, inspect existing tests and assertions, propose a new sequence, run a simulation, examine the results, invoke formal analysis and then recommend another experiment. T e individual engineering tools may
produce repeatable results for controlled inputs, but the orchestration around them introduces new sources of error. T e agent may select the wrong requirement, misinterpret a result, use an outdated design revision or stop aſt er obtaining evidence that appears suffi cient but is incomplete. T e verifi cation target therefore expands.
Teams must verify not only the design, but also the reliability of the AI-assisted path used to generate and interpret evidence.
Self-critique is not an independent check Large language models are oſt en asked to critique or refi ne their own output. T at can be useful, but it should not be confused with engineering verifi cation. A critical survey of LLM self-correction
found limited evidence that models reliably correct their own answers using only prompted self-feedback in general tasks. T e same survey found considerably stronger results where reliable external feedback was available, including tools and external knowledge. T at distinction maps directly onto
semiconductor verifi cation. An agent can say that an assertion looks correct. A formal engine can determine whether the
12 October 2026
www.electronicsworld.co.uk
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