Short Range Wireless


Easy digital filter applications for not-so- easy RF system designs


By Mitch Sternberg, system applications engineer, Analog Devices D


igital filters provide a meaningful way of controlling the input spectra of communication systems over a wide range of applications. They can filter


harmonics or isolate frequency bands to prevent intersymbol interference while saving you from the hassle of part procurement, PCB layout, and variations that come with their analogue counterpart. Of course, digital filters are not without flaw, but their elegance and ease of use in increasingly common mixed-signal environments make them a great choice for your systems’ filtering needs. Fear not the complexities of digital design; this article demonstrates a quick and easy method for implementing simple yet powerful digital filters for RF systems.


Digital filter basics


Both digital filters and analogue filters serve the same purpose - to ideally allow certain frequency components to pass through undistorted while completely attenuating all other frequencies. Digital filters accomplish this by summing and weighting discrete signal samples and performing this operation over the length of the input array.


in an FIR filter means sharper responses, flatter pass bands, and steeper transition bands. The main drawback of increased tap count is resources. Each tap represents time delay and computational resources, so when N grows large, so does the time delay and power consumption. FIR filters are inherently stable because there is no feedback used, and therefore no risk of driving an input that causes an output to compound and grow unbounded. FIR filters can also have a linear phase response, which makes them especially useful in RF applications where timing and group delay are important.


Let’s take a look at what implementing a digital filter would look like on a high-speed data acquisition platform. I will introduce the lab setup and how the results were verified, as well as go over the specifications of the system used. We’ll see what a real and practical digital filter produces for results when filtering both single tones and their harmonics, as well as multitone test vectors that demonstrate the filter profile over a larger band of frequencies. The scope of this article will not extend to applications of infinite impulse response (IIR) filters and will stay constrained to 192-tap filters with a sample rate of 1500MSPS.


Lab setup


The discrete implementation is shown in Equation 1 and is referred to as a finite impulse response (FIR) filter. More taps, N,


Figure 1. ADI’s AD9082 MxFE.


The platform used to demonstrate a real digital filter is Analog Devices’ AD9082 mixed-signal front end (MxFE). The data and results from the filter implementations are verified using


the platform’s loopback mode connected to a spectrum analyser. The AD9082 MxFE was set up for testing by interfacing with ADI’s ADS9 development platform for controlling the analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs), and to process the output data. A Rohde & Schwarz SMW200A vector signal generator was used to generate 5G-NR test vectors as well as single and multitone vectors, and a Rohde & Schwarz FSW was used to measure the output spectrum from the DAC.


The 192-tap FIR digital filter block (PFILT) is located directly after the ADC cores. To keep things simple, all tests shown in this article are run with one ADC channel being


48 November 2023 Components in Electronics


driven single-ended with all 192 taps enabled. The sampling rate of the system was set to 1500MSPS on both the transmit side and receive side; therefore, all spectra plotted will cover up to Nyquist, or (1500MHz)/2 = 750MHz.


Verification method


Figures 3 and 4 show a comparison between the ADC data and a spectrum analyser capture from the DAC outputs using an internal loopback. The spectral representation of these two signals is nearly identical, with a small variation in the noise floor due to the resolution bandwidth of the analyser. This step was done to confirm that the ADC data


www.cieonline.co.uk.uk Figure 2. A diagram of a test setup.


Figure 3. An ADC output. 200MHz to 5dBm RFIN.


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44  |  Page 45  |  Page 46  |  Page 47  |  Page 48  |  Page 49  |  Page 50  |  Page 51  |  Page 52  |  Page 53  |  Page 54  |  Page 55  |  Page 56  |  Page 57  |  Page 58  |  Page 59  |  Page 60  |  Page 61  |  Page 62  |  Page 63  |  Page 64  |  Page 65  |  Page 66  |  Page 67  |  Page 68  |  Page 69  |  Page 70