Semiconductors
communication infrastructures, data centres and high-end mobile phones. Advanced packaging techniques contribute significantly to this solution.
Of the three requirements to realize increasingly advanced silicon products (more transistors, more memory, and more interconnects between logic and memory), advanced semiconductor packaging technologies can be effectively utilized to accommodate for the increases to interconnections and memory. Specifically, chiplet design has emerged as a means to striking a balance between cost and performance. With regards cost, chiplets cater to a modular approach to building processors; different dies/chips are packaged together using the most appropriate process node. By reducing the use of the most advanced process nodes (which are more expensive than more mature nodes) where use of these advanced nodes is unnecessary, the total cost of the device is reduced.
Figure 2: IDM/Foundry logic node/process capabilities
keep their products competitive. Outsourcing can also mean more opportunities for newcomers, as they can design chips and get them fabricated by a foundry service without investing the unsurmountable CapEx for semiconductor fabrication. As autonomy proliferates, IDTechEx believes it likely that the automotive semiconductor supply landscape will shift over the next ten years. To learn more about semiconductor development trends, supply chain dynamics, and market outlook for automotive, please refer to IDTechEx’s report “Semiconductors for Autonomous and Electric Vehicles 2023-2033”
available online at
https://www.idtechex.com/
Advanced semiconductor packaging solutions for the data centre: development trends The most advanced semiconductor manufacturing process currently available is TSMC’s 3 nm process, which can create transistors with a density of 314.7 million transistors per square millimetre. This is a significant improvement over the chip’s transistor density from the 1970s, which was only a few hundred transistors per square millimetre. Advancement does not come
without a cost though, and in the case of advanced semiconductor manufacture, the cost is significant; it is projected that TSMC would need to ship more than 300 million chips before it starts making a profit due to the staggering initial CapEx of its 3nm technology. This, in addition to a demand for smaller devices – where compact integration of heterogeneous components and the need for higher interconnect densities is required – has given the industry cause to seek an alternate solution to manage costs while continuing to deliver advanced products, especially for high-end applications such as
Another driver for chiplet design is the need for more I/O (Input/Output). Packaging I/O dies (for example, SerDes, PCIEs, and memory I/O) on the same module as processing units utilizing 2.5D (shown in Figure 3, along with 3D packaging), allows for increased I/O counts in a system. 2.5D and above advanced semiconductor packaging is the only technology to enable sub-micron routing available today. Intel, NVIDIA, and AMD have all used advanced semiconductor packaging in their chips for HPC applications. Although 2.5D advanced semiconductor packaging technologies have already been deployed in a number of high-end commercial data centre chips, the development will go beyond that. Ultimately, the goal is to have complete 3D integration, where many logic ICs and memory are physically placed on top of one another. Finally, given the world’s expanding demand for data centres, advanced semiconductor packaging technologies will continue to play an essential role in driving the industry forward.
To learn more about advanced semiconductor packaging, including the technology developments, key players, and market prospects, including and beyond data centres, please refer to IDTechEx’s “Advanced Semiconductor Packaging 2023-2033” report. The full whitepaper – which includes further remarks on technology trends pertaining to advanced semiconductor packaging, automotive semiconductors and silicon photonics – can be found at:
Figure 3: The evolution of semiconductor packaging. Source: IDTechEx - “Advanced Semiconductor Packaging 2023-2033”
www.cieonline.co.uk.
https://www.idtechex.com/en/ research-article/key-semiconductor- technology-trends-for-data-centers- and-automotives/28647?content-
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