Frequency & Microwave


High speed oscillator design trends


Over recent years the electronics industry has moved from TTL to CMOS oscillator outputs, closely followed by LVCMOS as lower power considerations have become the prime driving force behind designs. Although the CMOS oscillator is the main workhorse of the industry, it does have severe limitations when it comes to speed and power. As frequencies rise, gate transition times are too slow for fast propagation so current consumption tends to increase proportionately and phase noise also rises. Andy Treble, sales & marketing director, Euroquartz Group tells us more


D


esire for even higher speeds, combined with better data integrity, has forced engineers to


develop LVDS /LVPECL formats. Comparing basic signalling levels for LVDS with those of PECL and TTL/CMOS, LVDS exhibits half the voltage swing of that of PECL and are approximately one tenth of traditional TTL/CMOS levels. However, LVDS and PECL oscillators also have limitations when it comes to phase noise and jitter in high speed circuits. The latest trend has seen a move


towards newer techniques such as HCSL and CML logic outputs which offer new benefits and advantages over previous output formats. The processing of increased amounts of data requires systems to run at much faster transfer speeds and this requires higher frequencies and faster transition times for oscillators.


Figure 1


High Speed Current Steering Logic (HCSL) offers a constant current characteristic which provides a less “noisy” solution compared with a static logic solution. This output offers a high impedance output with fast switching times and fitting a 10 to 30 series resistor will help to reduce any overshoot or ringing. This is a major benefit for mixed low voltage signal processing such as can be seen in optical communication, PCI express systems etc. The current consumption of HCSL generally lies between LVDS and PECL formats but offers faster speeds. This type of steering logic delivers a constant current output, with a 15mA current source the current is “steered” between the true and complimentary outputs. Current steering techniques have been used in bipolar technology with the sole objective of speeding up logic


Figure 2


gates. It should be noted that HCSL outputs require 50 termination as seen below in figure 1. Current Mode Logic (CML) offers a similar performance to LVPECL but lower power. Although they do not require external biasing, the downside is that they do require ac-coupling because they are unable to provide sufficient current to bias other devices as seen below in figure 2. The advantage is that CML offers lower output voltage swings compared to that of standard CMOS devices. This makes them ideal for low power applications and fast data speeds from 321.5Mbit/s to 3.125Gbit/s. and are used in such things as serial data transceivers, frequency synthesisers, etc. Data integrity is vital in all modern data transmission systems and this can seriously be affected by phase noise and jitter. Traditionally the best way to improve this performance characteristic was to use higher frequency fundamental crystals but there is a limit to the frequencies that are available and performance they can offer. Therefore LVDS, PECL, CML and HCSL oscillators have made big improvements in this area with phase jitter figures of 150fs now available. Careful consideration also needs to be given to the PCB layout when using these oscillators especially when it comes to routing differential signals around the circuit board. Differential traces should always be routed side-by- side, as this will keep any noise injection into the signal a true common-mode noise which normally gets rejected.


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If routing around another component, tracks must be routed together, never separately and it is important that the tracks are kept the same length. If not the same length, signals may arrive at the receiver at different times and cause significant performance issues. This is especially true for very fast switching digital signals and very high frequency analogue signals (>1GHz). Care should also be taken with the vias, it is known that the return current density follows the trace path directly under the signal trace. The current will always find a way to do this, one way or another, and the path it chooses may not be desirable. To minimise this return current flow path issue, every time a via is used, a ground via should also be utilised next to the signal via. This will allow the return current to flow near to the actual signal current flow. However, the via the signal flows through is like a cylinder that wants to have the return current flow 360° around it. If a single ground via is used for the return current, the characteristic impedance of the trace will be altered and may become an issue. There is no doubt that with ever


increasing amounts of data traffic, faster clocks offering better phase noise and jitter performance will be an increasing requirement that will continue to present challenges to oscillator manufacturers.


www.euroquartz.co.uk Components in Electronics June 2018 25


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