Interconnection
Evolution and challenges with copper interconnects: the crucial role of photonic package design
By Dr Larry Zu, CEO at Sarcina Technology C
opper interconnects have been used in semiconductor devices since the invention of integrated circuits (ICs) in the 1960s as the
conductive pathways that connect different components (such as transistors, capacitors and other elements) within ICs. These interconnects allow the electrical signals to travel between different parts of a chip, enabling the chip’s overall functionality. Although copper is a good electrical conducting material, copper interconnects can consume a lot of power and experience signal weakening at high frequencies – as demonstrated in today’s semiconductor devices at datacentres. Copper interconnects are effective over short distances but suffer from signal degradation, especially at high frequencies, when the distance exceeds a few metres. This is primarily due to increased insertion loss, skin effect and other forms of attenuation.
As the semiconductor industry continues to advance and chips are smaller, faster and more power-hungry, the problems with copper-based interconnects are becoming increasingly more apparent. Put simply, copper interconnects cannot deliver the high-performance requirements of HPC (high performance computing), datacentres and AI systems. Changes are needed to meet the evolving demands of modern times, and this is where photonic packaging comes into the conversation.
Co-packaged optics
There is growing interest in optical integration at the package level. Photonic integration technologies, such as silicon photonics, allow for the miniaturization of transceivers and enable co-packaged optics (CPO) or on-package optical I/O.
34 December/January 2026
CPO involves integrating optical fibres, used for data transmission, directly onto the same package or photonic IC die as semiconductor chips, such as CPUs, GPUs and network processors. The long copper trace between the switch and the optical
Components in Electronics
module is replaced with short, high- integrity connections between ASIC and optical module.
CPO has the potential to pave the way for advanced architectures, including chiplet-based systems and heterogeneous
integration, which are critical to delivering future AI systems. However, there are challenges with CPO. Designing photonic packages, especially for integrated photonic circuits or photonic chips, raises technical and practical issues.
www.cieonline.co.uk
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