FEATURE DIGITAL ELECTRONICS DESIGN COMING TOGETHER, IN
MEMORY OF: Cadence and
Adesto team up to enhance memory in IoT
T
he SPI is the short-range communications interface
through which the microcontroller or microprocessor in an embedded system talks to the various peripherals within it. This interface is a de-facto standard in the industry, having been developed in the 1980s by Motorola, and now used with sensors, control devices, camera lenses, communications, flash memory and other peripherals. Today, the flash memory devices in IoT
systems must often run code-intensive wireless stacks and support local artificial intelligence (AI) processing; this means they must support ever higher transfer rates and lower latency communications. Unfortunately, SPI has limited bandwidth available for code and data accesses between the processor and the external flash memory. In response to this, companies including Cadence and Adesto have joined together to define and establish hardware guidelines that enable designers to easily add high-throughput octal and quad devices to their systems. Expanding the flash SPI accesses from the traditional four I/Os (quad SPI) to eight I/Os (octal SPI), increases the serial NOR flash throughput and provides a more efficient solution for emerging applications. These guidelines have been defined by microelectronics standards body JEDEC, and released as the Expanded Serial Peripheral Interface (xSPI) communication protocol (JESD251).
“As two JEDEC members that helped drive the creation of the xSPI protocol, Cadence and Adesto are now focused on expanding the ecosystem around it”
18 NOVEMBER 2019 | ELECTRONICS The JESD251 standard defines several
techniques that enhance throughput, including the use of double data rate (DDR), where data is transferred on both clock edges, to provide a doubling of data throughput. It also includes the addition of a data-strobe signal that enables higher bus frequency, while transferring data at DDR. The combination of these techniques increases the available bandwidth by a factor of more than four. To decrease latency, the interface supports a special wrap-and-continue read command. This reduces the latency of fetching missing cache lines. When using this command, a series of instruction fetches can be fused into a single bus operation, eliminating the need for incurring the latency of separate commands for each instruction fetch. As two JEDEC members that helped drive the creation of the xSPI protocol, Cadence and Adesto are now focused on expanding the ecosystem around it. Adesto’s EcoXiP eXecute-in-Place (XiP) non-volatile memory (NVM) is a NOR flash device that supports this xSPI protocol. Elaboarting on Adesto’s technology, it means to eliminate the need for expensive on-chip embedded flash in a broad range of emerging IoT applications, while reducing power consumption for the sake of system cost and performance. Gideon Intrater, Adesto’s CTO, says, “Moving intelligence to the edge can provide significant advantages, but heavier local processing means that architects must revisit their system’s memory architecture. xSPI makes it easier for system designers to reap the benefits of octal devices, like EcoXiP, for efficient, user-friendly designs.” The new Cadence memory model for xSPI is a commercially available model that allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP NVM. The
IoT is on the rise: so are the demands on latency and speed of data transfer. So Cadence and Adesto, specialists in system design and IoT respectively, are looking to counteract these footfalls in contemporary embedded design, through the serial peripheral interface (SPI)
Adesto’s part to play in this comes in the EcoXiP, non-volatile memory flash device, for the purposes of supporting the xSPI protocol, as outlined by JEDEC
Cadence memory model for xSPI is part of the Cadence Verification Suite and is optimised for Xcelium Parallel Logic Simulation, along with supported third- party simulators. The suite is comprised of core engines and verification fabric technologies that support the Cadence intelligent system design strategy, enabling SoC design.
According to David Peña, verification
IP product management director of the system and verification group at Cadence, “Support for new protocols, such as xSPI, is critical for standard adoption and will help enable a new class of IoT devices. The availability of the memory model for Adesto’s EcoXiP, and host controller design IP for xSPI devices, enables joint customers to quickly and easily adopt xSPI while developing their products.” Intrater agrees: “The Cadence memory model will help our EcoXiP customers to optimise their systems even more.”
Adesto Cadence
www.adestotech.com
www.cadence.com / ELECTRONICS
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