FEATURE POWER ELECTRONICS


DESIGNING ACTIVE CAPACITOR DISCHARGE FOR POWER-RAIL SEQUENCING


Ian Milne, Diodes Inc. explores the latest techniques for enhancing power system design M


any of today’s processors and system- on-chip ICs have multiple power rails,


which must be started in a defined sequence to ensure correct system operation. Powering down in the exact reverse sequence can be equally important, to prevent damage to components. A power-sequencing controller is usually used, but extra circuitry is needed to discharge the decoupling capacitors on individual voltage rails at a known rate to ensure proper control of the power-down sequence. An active-discharge circuit inserts a resistance in series with the capacitor during power-down, such that the combined RC time constant controls the discharge time. The resistance value must be chosen to avoid excessive current and noise, but to discharge the capacitor to 5% of its voltage quickly enough for all rails to power down within an acceptable time.


CIRCUIT DESIGN Figure 1 illustrates a practical active- discharge circuit. When the sequencer output goes low to disable the regulator, Q1 inverts the signal thereby turning on Q2 to discharge the capacitor through R2. R2 determines the active-discharge time constant and also prevents sharp rising current peaks that could cause EMI issues and transient thermal stress on both Q2 and the capacitor bank. Q1 is selected by referring to the output- voltage threshold of the power sequencer. It should have a high enough VGS(th)


to remain


turned off when the sequencer output is high, bearing in mind that VGS(th)


falls with


increasing junction temperature. The ZXMP6A13F MOSFET shown has a minimum VGS(th)


of 1V at room temperature and about


0.9V at 60°C. The 100kΩ resistor pulls the gate down to source potential to avoid false turn-on. When calculating R2, the RDS(ON)


of Q2,


parasitic trace resistances, and the ESR of the decoupling capacitors must be considered part of the discharge resistance. Assuming the sequencer must turn off a total of 1ten power rails within 100ms, the capacitor bank on each must be discharged in less than 10ms. A 3x RC time constant of 8ms is enough to discharge the capacitance below 5% of its full voltage within the required time. Assuming the capacitor ESR and trace


22 MAY 2016 | ELECTRONICS


ASSESSING MOSFET SOA Because the DMN3027LFG will dissipate the capacitor’s energy as a function of both current and voltage over time, its Safe Operating Area (SOA) at the application’s ambient operating temperature (60°C) with the required VGS


resistances combined do not exceed 10mΩ, and the total decoupling capacitance is 15mF, suitable values for RDS(ON)


and R2 can be


calculated from: 3 x (10mΩ + R2 + (1.5 x RDS(ON


RDS(ON ))) x 15mF =


8ms Assuming R2 = 50mΩ, Q2 must have ) less than 80mΩ (at VGS = 4.5V


and 25˚C ambient temperature). The effects of temperature-related change and lot-to-lot variation on the RDS(ON RDS(ON


Figure 1:


The active capacitor- discharge circuit


must be assessed. To discharge the 0.9V charged capacitor bank, an acceptable SOA curve should indicate single-pulse peak-current capability of at least 1V for pulse widths between 1ms and 10ms when mounted on ordinary PCB with minimal heatsinking (known as minimum recommended pad (MRP) layout). Power dissipation in both Q2 and R2 under worst-case conditions should also be considered. For example if the power sequencer were to enter a continuous loop, charging and discharging the capacitor bank’s total stored energy every 20ms (10ms enable + 10ms disable), about 0.5W would be dissipated across Q2 and R2: P = E ÷ t = ½CV2 ÷ 20ms = 500mW (assuming C = 20mF charged to 1V) Since the DMN3027LFG’s maximum ) is 40mΩ,


temperature-adjusted RDS(ON


222mW is dissipated in R2 and 278mW in Q2. At the lowest RDS(ON


) of 15mΩ, R2 ) of Q2 should also be considered.


) can vary by as much as 15mΩ over the expected operating temperature range at 4.5V VGS. Hence R2 should be about double the manufacturer-specified maximum RDS(ON


) of the chosen MOSFET.


If R2 is 50mΩ, choosing the N-channel DMN3027LFG for Q2 limits RDS(ON


) to


about 15-40mΩ over temperature range. This gives 95% (3x RC) discharge time of between 3.9-5.4ms with a worst-case capacitor bank of 20mF.


dissipates 385mW. Hence a 0.5W resistor is required. The DMN3027LFG has junction-to-


Figure 2:


Active discharge without (left) and with (right) 50mΩseries resistor


ambient thermal resistance (RθJA) 130°C/W on MRP layout. If the ambient temperature is expected to reach 60°C, then TJ reaches 90°C when dissipating 222mW. This is well below the TJ(max) of 150°C. A 13.2mF nominal capacitor bank and an active discharge circuit, comprising the ZXMP6A13F P-channel MOSFET (Q1) and DMN3027LFG N-channel MOSFET (Q2), was assembled as in figure 1. Q1 was manually triggered with a 5V signal. First, the capacitor bank was discharged through only the DMN3027LFG. Figure 2 shows the peak current reaches about 30A. This reduces at higher temperature as the MOSFET RDS(ON) increases. With R2 in circuit the peak discharge current reduces to about 12.5A. Temperature dependence is also reduced. The discharge time is 3 to 4ms, which is close to the figure calculated from theoretical values.


Diodes Inc.


www.diodes.com T: +1 0161 622 4444


/ ELECTRONICS


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