FEATURE EDA The next wave of analogue and system design
Cadence recently announced a new version of its Virtuoso Design Platform, called ICADVM18.1. This release has focused on creating advanced methodologies and solutions that rely on the integration of multiple tools to work together to solve the inherent challenges across multiple design domains. Yuval Shay, director of product management, Cadence has more on this next wave of system design
and custom designs, its is prudent to perhaps consider new, advanced IC design methodologies in order to increase productivity, increase the amount of design robustness and take advantage of automation to reduce the overall turnaround time (TAT). With ICADVM18.1, Cadence is introducing a range of automation technologies to help speed design creation processes through to signoff.
C
ustomers are evolving and becoming more system focused. Cadence sees
this with its IC customers building themselves up to provide more complete packages, and with its system customers who wish to develop more IC designs they depend on. To meet this demand, the company needs to provide solutions that address the challenges of complex integrated systems, regardless of how its customers approach the development. With the release of its new Virtuoso design platform, the company has focused on three main areas: enhancing the system design platform, extending its advanced-node solution, and propagating advanced IC design and flow automation techniques.
ENHANCING SYSTEM DESIGN In May 2017, Cadence introduced its Virtuoso System Design Platform (VSDP) and this solution is in production at a number of its customers. This tool has illustrated a growing need by the company’s customers to streamline the design flow across chip, package and board. They told Cadence that it’s not enough to design a chip in isolation from the package and board. The dependencies between board, package and chip must be captured early on. In this release of the tools, the
company has enhanced the interoperability between its SiP solution and Virtuoso design platform, adding the capabilities to edit SiP modules using the Virtuoso Layout Suite and a smart integration of its Sigrity 3D-EM Finite Element (FEM) Solver.
24 JUNE 2018 | ELECTRONICS Figure 1:
Enhanced Virtuoso design platform ICADVM18.1 innovation for the next wave of analogue system design
EXTENDING THE ADVANCED-NODE SOLUTION This new release supports all nodal technologies and process geometries, including the most advanced process node down to 5nm. To make sure its design tools and applications are ready for new design challenges, Cadence is working with leading foundries, and it is also working with the Cadence IP Group to develop solutions for advanced-node custom design. The Virtuoso advanced-node solutions
offer users a multi-grid layout system that abstracts the layout complexities inherent in those technologies. This enables a much greater use of automation thereby significantly increasing design productivity. In addition, the Virtuoso Variation Option contains advanced statistical algorithms specifically targeting FinFET designs that uncover circuit variances early, allowing correction long before the variances manifest themselves in the completed design. With the increase in design content and the growing complexities of analogue
Figure 2:
The improved integration of Spectre simulation with the new Virtuoso ADE environment enables higher
simulation throughput and smarter simulations with advanced statistical algorithms in order to uncover circuit variances earlier in the process
A FEW EXAMPLES For the first time the company is introducing simulation-driven layout capabilities during the design phase to help address current density and parasitics concerns that may lead to electromigration (EM) failures. This new set of features uses simulation data to drive implementation, for a true correct- by-construction layout. The Virtuoso Design Planner provides a new set of layout planning features, based on a robust layout environment, to help manage the layout hierarchies, floorplan the design and plan nets for routing. These new features can help guarantee routing convergence and drive better utilisation of area. Another new feature is the concurrent
layout design and non-destructive editing technology that allows multiple users to edit the same hierarchy (cellview) simultaneously. This new use model not only enables something termed “non-destructive editing”, but in addition, gives control to the cellview owner to accept or reject edits from other users and to add notes, in case edits get rejected. The Virtuoso ADE Verifier bridges the divide between the top-level specifications and standards and the actual test implementations created by the analogue design engineers. By tracking your analogue coverage in one single, constantly updated location, you will be able to know the overall progress of the design and when you actually have completed all of your specification verification tasks.
Cadence
www.cadence.com T: 01344 865 444
/ ELECTRONICS
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