ARTIFICIAL INTELLIGENCE
Redefi ning memory for AI: High-bandwidth, low-latency solutions for next-gen computing
A
s High-performance computing (HPC) workloads grow more complex, generative AI is becoming increasingly integrated into modern systems, driving demand for advanced memory solutions. To keep pace with these evolving requirements, the industry is developing next-generation memory architectures that maximise bandwidth, minimise latency and enhance power effi ciency. Advances in DRAM, LPDDR and specialised memory solutions are redefi ning computing performance, with AI-optimised memory playing a central role in driving effi ciency and scalability.
Advanced memory architectures and performance scaling
Memory technology is advancing to meet the stringent performance requirements of AI, AIoT and 5G systems. The industry is witnessing a paradigm shift with the widespread adoption of DDR5 and HBM3E, offering higher bandwidth and improved energy effi ciency. DDR5, with a per-pin data rate of up to 6.4 Gbps, delivers 51.2 GB/s per module, nearly doubling DDR4’s performance while reducing the voltage from 1.2V to 1.1V for improved power effi ciency. HBM3E extends bandwidth scaling, exceeding 1.2 TB/s per stack, making it a compelling solution for data-intensive AI training models but impractical for mobile and edge deployments due to excessive power requirements.
With LPDDR6 projected to exceed 150 GB/s by 2026, low-power DRAM is evolving towards higher throughput and energy effi ciency, addressing the challenges of AI smartphones
and embedded AI accelerators. Winbond is actively developing small-capacity DDR5 and LPDDR4 solutions optimised for power- sensitive applications while pioneering CUBE memory, which achieves over 1 TB/s bandwidth with a signifi cant reduction in thermal dissipation. With anticipated capacity scaling up to 8 GB per set or even higher, such as 4Hi WoW, based on one reticle size, which can achieve >40GB density and bandwidth >40TB/s, CUBE is positioned as a superior alternative to traditional DRAM architectures for AI-driven edge computing. Besides that, the CUBE subset is CUBE-Lite, which can offer 8GB/s (equal to LPDDR4x x16 B/W), and the operation power is 30 per cent of LPDDR4x. Furthermore, SoC w/o LPDDR4 PHY and only CUBE-light controller, SOC w/
smaller die size and good system power. The architecture is an AI-SoC (MCUs+MPUs+NPUs), a TinyML Endpoint AI device that shoots for battery. The system OS is Micro Linux + an AI model for AI-Soc. The end application is AI-ISP for IP-cams, AI glasses, or wearable devices.
Memory bottlenecks in generative AI deployment
The exponential growth of generative AI models creates unprecedented memory bandwidth and latency constraints. AI workloads, particularly those relying on transformer-based architectures, require extensive computational throughput and high-speed data retrieval.
For instance, deploying LLamA2 7B in INT8 mode requires at least 7 GB of DRAM or 3.5 GB in INT4 mode, highlighting the limitations of conventional mobile memory capacities. Current AI smartphones leveraging LPDDR5 (68 GB/s bandwidth) face signifi cant bottlenecks, necessitating a transition to LPDDR6. However, interim solutions are required to bridge the bandwidth gap until LPDDR6 commercialisation.
At the system level, AI edge applications in robotics, autonomous vehicles and smart sensors impose additional constraints on power effi ciency and heat dissipation. While JEDEC standards continue evolving toward DDR6 and HBM4 to improve bandwidth utilisation, custom memory architectures such as Winbond’s CUBE provide scalable, high- performance alternatives that align with AI SoC requirements. CUBE integrates HBM-level bandwidth with sub-10W power consumption,
12 OCTOBER 2026 | ELECTRONICS FOR ENGINEERS
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