Data acquisition
How to design a programmable gain instrumentation amplifier for precision wide bandwidth signal chains
By Maithil Pachchigar, systems application engineer, and John Neeko Garlitos, product applications engineer, both with Analog Devices
This article aims to help hardware designers with the design of wide bandwidth programmable gain instrumentation amplifiers (PGIAs) from the selection of off-the-shelf discrete components to performance evaluation and how to save time and reduce design iterations. The PGIA architecture presented is optimised for driving the high precision successive approximation register (SAR) architecture-based signal chain at full speed. The article also demonstrates the PGIA’s precision performance in driving wide bandwidth signal chains for various gain options.
synthesize and drive. Hardware designers developing these data acquisition signal chains typically require high input impedance to allow direct interface with a variety of sensors. In this case, a programmable gain is often needed to adapt the circuit to different input signal amplitudes - unipolar or bipolar and single- ended or differential with varying common-mode voltages. The majority of PGIAs traditionally consists of a single-ended output that cannot directly drive a fully differential, high precision SAR architecture- based signal chain at full speed and may require at least one signal conditioning or driver stage. Industry dynamics have been rapidly evolving with increased focus on system software and applications to differentiate system solutions. There is less time to build and prototype analogue circuits to verify their functionality due to tight R&D budgets and time to market constraints. Hardware development resources are put under increased pressure to reduce design iterations. This article focuses on the key aspects of designing a discrete wide bandwidth, fully differential PGIA and demonstrates its precision performance when
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driving a high speed signal chain µModule data acquisition solution.
PGIA DESIGN DESCRIPTION Figure 1 shows the discrete wide bandwidth, fully differential PGIA simplified circuit block diagram. The key specifications and design requirements for this PGIA circuit are listed in Table 1.
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precision data acquisition subsystem typically consists of high performance, discrete linear signal chain blocks to measure and protect, condition and acquire, or
This discrete PGIA is built using the following components:
ADA4898-1 low noise, high speed amplifiers
LT5400 quad matched resistor network, used as gain and feedback resistors to set PGIA gain
ADG1209 low capacitance, iCMOS multiplexer to control PGIA gain
ADA4945-1 wide bandwidth, fully differential amplifier (FDA)
The discrete components for this wide bandwidth PGIA circuit were chosen to meet the PGIA specifications highlighted in Table 1 and achieve an optimised AC and DC performance when driving fully differential high speed signal
chain µModule data acquisition solutions such as the ADAQ23875 and ADAQ23878, and ADCs
such as the LTC2387-16/LTC2387-18.
DESIGN TIPS AND COMPONENTS SELECTION
The ability of this wide bandwidth discrete PGIA solution to drive high speed SAR architecture-
based signal chain µModule solutions and achieve optimised performance is dependent on the key specifications (such as bandwidth, slew rate, noise, and distortion) of the amplifiers as well as the FDA. The ADA4898-1 and the ADA4945-1 were chosen because their gain bandwidth (GBW) products support the overall bandwidth requirements of this signal chain. The ADA4945-1 (FDA) is only required when driving ADCs such as the LTC2387-16/LTC2387-18. The criteria for setting the PGIA gain are dependent on the selection of amplifiers, feedback resistors, and multiplexers, as discussed in the next section.
Figure 1. A simplified PGIA circuit block diagram. November 2022 Instrumentation Monthly
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