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generally small enough that it does not affect circuit performance. Deterministic jitter is typically repetitious and can be classified as either periodic or data-dependent. For example, jitter caused by a switching power supply is periodic because it matches the switching frequency used. Data-dependent jitter can be either periodic or aperiodic and is caused by the changing duty cycles and irregular clock edges of a coded serial data stream in Ethernet or PCIe systems. Data- dependent jitter can be difficult to trace because it is system dependent. Jitter is usually classified in one of three ways - absolute, period, and cycle-to-cycle. Absolute jitter, sometimes also referred to as time interval error, (JTIE) is the difference in time between when the leading edge of a real clock occurs and its theoretically calculated value. Period jitter (Jper) is the difference between the longest and shortest duration of a clock period over a fixed number of cycles (Figure 3) while cycle-to-cycle jitter (Jcc) is the maximum difference between consecutive clock periods measured over a fixed number of cycles.
EFFECTS OF JITTER Excessive jitter can be detrimental to circuit performance. In synchronous ethernet (SyncE) and optical transport networking (OTN) applications, JTIE causes loss of synchronization which is critical for their proper operation. Jper and Jcc are important in digital applications because they affect the set-up and hold time of latches and flip flops, they reduce the sampling interval of precision ADCs which in turn places a limit on how fast a digital processor can operate. Tight control of Jcc is also important in applications that cannot tolerate changes in clock frequency (Figure 4).
OVERCOMING JITTER Jitter can be minimised by the application of good design practices. As a starting point, it is important to remember that every electronic device introduces intrinsic jitter to a circuit, therefore it makes sense to reduce the number of devices being used if practical. Designers should also be careful not to over-specify the jitter requirement for a circuit, since most circuits can operate properly even with some jitter present. To reduce costs when designing a clock-tree, it is tempting to use fewer crystals and clock generators and instead use more clock buffers, but this makes overall system timing less precise. Timing accuracy can be further improved by using VCXOs and zero delay buffers, but these increase design complexity. Other common design techniques to help meet the timing budget include keeping signal lines short (to reduce clock tree latency), using carefully matched components, matching clock line lengths and using spacing and shielding to prevent unwanted signal crosstalk. While these are good practice, they do not always guarantee satisfactory timing performance. EMI, voltage fluctuations, and mechanical stress (which affects the piezoelectric characteristics of the crystal) also contribute to jitter. If jitter continues to be problematic, it may be
Instrumentation Monthly November 2022
Figure 1(above) Clock tree using multiple clocks from a combination of a single crystal and a clock generator. (Source: Silicon Labs)
Figure 2 (above) Clock generators reduce the number of components on a board. (Source: Silicon Labs)
Figure 3 (above) Period jitter is the difference between the longest and shortest clock cycles over an observed duration. (Source: Silicon Labs)
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