Automotive & motorsport
input voltage, L is inductance value, and FS is the switching frequency.
Replacing the DL with CL that has a leakage inductance LK and the mutual inductance LM, the current ripple in CL can be shown as Equation 4.6 The term defined as figure of merit (FOM) is expressed as Equation 5, where NPH is the number of coupled phases, is a coupling coefficient (Equation 6), and j is a running index, which just defines an applicable interval of the duty cycle (Equation 7). The parameters of the CL are the leakage inductance LK and the mutual inductance LM.
Figure 2. Developed NCL0804-4-R17 (h = 4 mm max).
technologies where both current ripple and transient slew rate are arbitrarily different from the DL equations (for example, TLVR9).
The meaning of FOM in equations 4 and 5 for the particular CL design can be interpreted as an additional multiplier in current ripple cancellation as compared to the conventional buck with discrete inductor L. The definition of FOM and its meaning were also generalised and extended11 to compare any systems with arbitrary current ripple and transient performances. The proposal is to use a ratio of the normalised transient spew rate (desired high) to the normalised current ripple (desired low) (Equation 8). The transient slew rate and the current ripple are normalised by related numbers for some benchmark converters with discrete inductors (so any system with DL will still lead to FOM = 1). The SRTR and ΔIL are transient current slew rate and current ripple in a steady state of the chosen design or technology, while SRTR_DL and ΔILDL are the same parameters but for the benchmark DL design.
Equation 8 can be simplified into Equation 9, using the fact that the current slew rate for the discrete inductor is the same in transient and steady state. This way, any actual reference to DL design is completely removed, while the benchmarking ideology is still there.
Notice that using the generalised FOM definition, Equation 9, for the CL will result in Equation 5, so the new definition is backward compatible, but can also be used for
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CL DESIGN AND CONSIDERATIONS The application specifications are VIN = 5 V, VOUT = 0.8 V, FS = 2.1 MHz, and NPH = 8. As a starting point, DL = 32 nH is chosen to support the fast transient, while each inductor occupies 4.2 mm × 4.2 mm × 4.2 mm. Ideally, these would be substituted with an 8-phase coupled inductor (CL). However, the low height requirement of h = 4 mm presents a challenge, as it would make such a lengthy component unmanufacturable due to being excessively thin and long, while also increasing sensitivity to board flex. Therefore, the 4-phase building block was chosen for CL. This also enables better flexibility with placement and layout. As the faster transient is targeted and knowing that the CL will have smaller ripple than the starting DL value, the recently introduced Notch CL (NCL) structure was proposed to minimise the leakage value LK.7,8,10 The NCL0804 was designed with LK~17 nH and OCL = LM + LK = 100 nH, NPH = 4, phase pitch 6.9 mm/phase, and a height h = 4.0 mm max (Figure 2). A good way to compare different designs is a FOM plot.10 Any DL design will have FOM = 1, as the trade-off between the current slew rates in steady state and transient is 1:1. The NCL structure of the coupled inductor maximises LM/LK ratio in a given size, so it generally results in the highest FOM.9 The FOM comparison is shown in Figure 3, where the developed NCL is ~4.4× better than DL around the targeted output voltage. The corresponding current ripple comparison is shown in Figure 4 and Table 1. While the DL value can be chosen in a wide range for a different compromise between current ripple and transient slew rate, the advantage of developed NCL is always 4.4×. This correlates to 2.35× smaller current ripple than the ripple of DL =
32 nH while NCL is 1.88× faster. Then 2.35 × 1.88~4.4, matching the predicted FOM = 4.4. The current ripple can also be lowered a lot by using DL = 100 nH, which makes it 1.33× smaller current ripple than that in NCL, but NCL is then 5.88× faster, resulting in the same 5.88/1.33~4.4× advantage of NCL over any DL (FOM = 4.4 for NCL).
Looking at a theoretical FOM for the same NCL in Figure 3 but considering if NPH = 8 is manufacturable: the performance advantage of NCL over DL would increase from 4.4× to 5.8×, and make even more relative difference at a lower VOUT.
Looking ahead, it might be worth considering a different design for the NCL. One possibility is arranging the phases in two rows to maintain a low aspect ratio (length/height) of the ferrite core, making it conducive to manufacturing. In this scenario, the NCL could potentially be positioned at the bottom of the PCB, directly above the ceramic bypass for the GPU, with power stages surrounding the NCL on the perimeter. The approach, akin to a vertical power delivery (VPD) arrangement, could potentially
Figure 3. FOM for the developed NCL = 4× 17 nH and theoretical NCL = 8× 17 nH as a function of the output voltage VOUT compared to the FOM of any DL (VIN = 5 V).
February 2025 Instrumentation Monthly
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