Sensors & transducers The switch positions shown in Figure 7


correspond to the sampling or acquisition mode where the analogue input is connected


to the sampling cap CDAC before conversion begins on the next phase of operation. Prior to the start of this phase, switch S2


has discharged CDAC voltage to 0 V or other bias point such as FS/2. At the start of the


sampling period when S1 closes and S2 opens, the difference in voltage between VSH and the analog input causes transient current


to flow so that CDAC can charge toward analogue input voltage. This current can be as large as 50 mA for higher sampling rate ADCs.


Capacitor CEXT helps to mitigate the step change in the amplifier output voltage because of this current step, but the amplifier is still subjected to its disturbance and needs to settle in time before the end of the acquisition


period. Resistor REXT isolates the driver from CEXT and also reduces the impact on stability when driving a heavy capacitor. The choice of


values for REXT and CEXT is a trade-off between more isolation from this current


injection and degradation of settling time due to the low-pass filter formed this way. This filter can also help reduce the out-of- band noise and to improve SNR, although that is not its main function.


ADC Front-EnD rC ComponEnt VAluE DEsign


Many considerations go into the choice of


values for REXT and CEXT Here is a summary of factors that affect the ADC dynamic response as measured by FFT or other means:


CEXT: Acts as a charge bucket from the input charge kickback that occurs to


minimise the voltage step and thus improve settling time.


■Too large: It may affect amplifier stability and could lower the LPF roll-off frequency too low to pass the signal.


■Too small: The charge kickback from the ADC input becomes too large to settle in time.


REXT: Provides isolation between the amplifier output and CEXT to ensure stability.


Where:


■Too large: It may make the settling time constant too long. May also cause a THD increase when looking into the ADC input nonlinear impedance. Can increase IR drop error.


■Too small: Amplifier may become unstable or its forward path settling may be compromised due to CEXT.


Here are a few design steps to design the


REXT and CEXT values using an LT2367-16 ADC, as an example, driven by an LT6372-1


36


VSTEP:ADC input voltage step calculated earlier


VHALF_LSB: LSB/2 size in volts.With 5V FS and 16 bits, that’s 38 µV (= 5V/217) → NTC = 6.4 time constants


Calculate the time constant, τ: Where:


tACQ:ADC acquisition time; tACQ = tCYC – tHOLD


Where:


VREF = 5V (LTC2367-16) CDAC:ADC input cap = 45 pF (LTC2367-16)


CEXT = 10 nF (from earlier) →VSTEP = 22 mV (calculated)


Note: This VSTEP function assumes that CDAC is discharged to ground at the end of each sample period, as is the case with LTC2367-16.


The VSTEP formula in Reference 1 has a different assumption in that it is for ADC


architectures where CDAC voltage is maintained from sample to sample.


Compute how many input REXT × CEXT time constants, NTC, are required to settle, assuming exponential settling of the step input:


Figure 8. ADC external input RC relationship for proper settling.


Use the previous steps to find suitable


REXT and CEXT starting values. Bench testing and evaluation should be performed and


these values optimised as needed while keeping in mind the impact of such changes on performance.


summAry


A new family of instrumentation amplifiers was introduced to help bridge the gap between a transducer and data acquisition. The features of these devices were explored in detail along with a real-world example of how to design the ADC front-end components to ensure that the driver plus ADC combination can deliver the resolution intended.


Analog Devices www.analog.com February 2021 Instrumentation Monthly


with a 2 kHz max input frequency, fIN, at a sampling rate of 150 kSPS:


Choose a CEXT large enough to act as a charge bucket to minimize the charge


kickback:


Where: CDAC:ADC input capacitance = 45 pF (LTC2367-16) → CEXT = 10 nF (selected)


Compute the ADC input voltage step VSTEP using:


Assume sampling rate of 150 kSPS:


tCYC = 6.67 μs (= 1/150 kHz) tHOLD = 0.54 μs (LTC2367-16)


thus: tACQ = 6.13 μs → τ ≤ 0.96 µs


With τ and CEXT known, REXT can be computed:


→ REXT ≤ 96 Ω We now have the external RC values that


allow proper settling for the chosen ADC. If


the computed REXT is too high, CEXT can be increased and REXT recalculated to reduce its value, and vice versa. Figure 8 shows the value


of REXT for a chosen value for CEXT to simplify this task when operating under the conditions


of this example.


Figure 7. SAR ADC input in acquisition/ sampling mode.


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