• • • TEST & MEASUREMENT • • •
SDT can also accelerate product release cycles, speeding time to market. With traditional wafer probing, a few bad dies can hold up a complete wafer as engineers study yield problems and determine how to fix them. With SDT, bad dies can be held back for study, but good dies can immediately proceed on to packaging and final test and on to customers. Traditional wafer probing is also subject to probe-burn concerns that arise when touching down on multiple dies, especially in the early phases of a new design or process node. SDT can also avoid the silicon defectivity problems that compromise multi-site probe test efficiency by matching a good die.
Die-level handler
Equipment that can address the challenges of singulated die test includes the Advantest HA1200 die-level handler, which, when equipped with an active thermal interface (ATI), can be used in conjunction with test systems such as the Advantest V93000 SoC tester. The combination can enable the test of high-end SoCs with excellent test coverage, helping to reduce yield loss at the final test of multi-die assembled products. Figure 3 shows the HA1200 (left) and a 100-W/cm2 quad- site active thermal interface for testing CPU chiplet dies. When used with the V93000, which sits on top of the HA1200’s die alignment unit (right-side module below), the handler and thermal interface can obtain a thermal profile to enable comparison with the thermal profiles at wafer sort and at final test.
SDT allows customers to respond to temperature changes very quickly, and Advantest has been involved in studies in this area. In particular, customers have CoWoS and similar advanced package assemblies, and many defects in such structures do not appear until after the singulation process, which applies mechanical stress to each die. Furthermore, temperature stresses for singulated dies can be greater because each singulated chip cannot rely on the mass of the entire wafer, which provides mechanical strength and thermal dissipation. The combination of mechanical and thermal stresses increases the chances of faults at the die-to-die interconnects, whether in CoWoS assemblies or HBM stacks. The latter continues to present yield challenges as stack heights continue to grow.
There are several benefits to singulated die tests. The main focus is on temperature response, the ability to regulate thermal excursions during a wafer-sort insertion by mimicking the final-test conditions. Some Advantest customers have a discrepancy between final-test temperature and wafer-sort temperature set points because the wafer-probe environment has been more challenging.
The singulated die probe allows better control to mitigate the thermal excursions and probe burn risk that are more common with typical chuck- based probe insertions. With the rise of chiplet technology and stacked-die use, it is increasingly likely that good dies can be mixed with bad dies, resulting in good dies, substrates and interposers being discarded.
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current, voltage, and junction temperature; an HA1200 die-level handler configured with two generations of the company’s ATI thermal solution; and a V93000 tester programmed to test a 6-nm CPU chiplet die.
The study involved manual execution of a single test-site V93000 test flow on a quad-site die-probe setup using a hot temperature setpoint, and it compared the temperature profiles of a hot- temperature wafer-sort insertion, a hot- temperature package-test insertion, and two hot- temperature SDT insertion. Figure 4 shows the peak temperature excursion and the time to guardband for the wafer-sort hot test, two test setups for the SDT hot test (Thermal setup #1 with the Gen 1 ATI solution and Thermal setup #2 with the Gen 2 version), and the final package test hot test.
Further work Work remains to be done on effectively implementing SDT. For example, customers are very interested in applying SDT to achieve SoCoW-assembly quality improvements. Also of interest are new, larger Advantest thermal interfaces that can dissipate more heat. Work needs to be done evaluating these interfaces based on customer data, as power density increases with future process nodes. In addition, work is proceeding on multisite efficiency gains and quad-site thermal evaluation, as well as on studying post-singulation yield and defectivity. Finally, customers are evaluating when and for what devices SDT is most effective. Most customers are expected to continue with the Wafer Sort 1 cold test, but they could consider replacing the Wafer Sort 2 chuck-based test with SDT, allowing closer tuning with final-test results. These customers must evaluate trade-offs between yield gains and disruption to their standard test processes and the capital investment involved. Considerations will include factors such as total test time and the average selling price of the device under test. For many customers producing singulated chip on wafer structures, SDT will very likely pay for itself.
Figure 3. An Advantest study employed an HA1200 handler (left) and a 100-W/cm2 quad-site active thermal interface (right).
A specific study conducted by Advantest included an analog-to-digital converter attached to the probe load board to capture profiles of device
Advantest’s HA1200 handler equipped with ATC has demonstrated the ability to precisely regulate temperatures, allowing a singulated die test to simulate final-test conditions. An Advantest study has demonstrated that SDT is effective in controlling temperatures as process geometries shrink and power densities rise for HPC and AI devices with HBM stacks and CoWoS structures.
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Figure 4. The Advantest study recorded peak temperature excursion and the time to guardband for the wafer-sort (WS) hot test, two test setups for the SDT hot test, and the final-test (FT) hot test.
ELECTRICAL ENGINEERING • MARCH 2026 15
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