• • • TEST & MEASUREMENT • • •
SINGULATED DIE TEST ENSURES STACKED DIE QUALITY AS POWER DENSITY RISES
Power-density growth Figure 1 shows an estimate of power density’s dramatic growth in the HPC/AI era.
BY BRENT BULLOCK,
TEST TECHNOLOGY DIRECTOR, ADVANTEST AMERICA
Shrinking geometries combined with increased design complexity with respect to metrics such as gates per square micrometer, plus higher operating frequencies, are leading to ever higher levels of power density.
T
The resulting device thermal excursions are driving the need for singulated die test (SDT) with active thermal control (ATC), which combine to boost yields and ensure the quality of the chiplets and other die that make up multichip packages for high-performance computing (HPC) and artificial- intelligence (AI) server farms.
SDT detects defects that do not appear until
after singulation, which are most often faults in chip-to-chip interconnects. SDT can also improve device handling efficiency, so it is applicable to multiple test scenarios, with test content varying accordingly:
• Die-probe insertion using Final-Test conditions • Die matching and die-bank rescreening • Complex chip-on-wafer/ known-good assembly testing
• Extended yield learning • Silicon-photonics optical-engine testing 14 ELECTRICAL ENGINEERING •MARCH 2026
Figure 2. Temperature excursions ( Temp) increase as process technology shrinks.
The high power density in turn produces large thermal gradients, with the low to max temperature changes increasing dramatically in both mission
Figure 1. Power density has accelerated throughout the HPC/AI era.
he accelerating rate at which the industry adopts new process nodes is posing critical test challenges.
mode and test mode as process geometries shrink, as shown in Figure 2. These large temperature gradients lead to increased yield loss due to challenges in maintaining the set temperature. Consequently, Advantest customers are taking steps to monitor and control the thermal gradients and respond to the temperature excursions from the wafer-sort level through the final test. However, the ability to control thermal behavior during various test insertions has been problematic, requiring close attention to the thermal interfaces and differing thermal masses. Thermal control at wafer sort traditionally has been very limited, because a single large chuck, historically with just a single sensor in the middle of it, provides temperature control. Subsequent chuck configurations included multiple sensors in multiple zones, approaches that did provide some relief and drove yield improvements. Package testing also presents challenges, because the package itself, potentially with a lid, adds thermal mass. So many customers feel they need to move to more aggressive thermal-control solutions at die sort.
Die-probe insertion Die-probe insertion offers one solution, with thermal control required for only a small piece of the wafer, the singulated die, allowing thermal interfacing directly without a lid, so the thermal mass is very low and the thermal characteristics very different. With the arrival of high-power- density devices, SDT, which has existed since about 2015 but has found limited adoption, is now gaining interest.
electricalengineeringmagazine.co.uk
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44
