MCUs & MPUs
aspect ratio etches and the fragility of the fins under the high stress necessary for mobility enhancements are further factors driving high restrictions.
A FinFET manufacturability rule (to alleviate severe performance consequences) worth mentioning specifically is the rule associated with “lonely” FinFETs. Given the 3D nature of the fins, the SiGE stress profile of a P- device loses all effectiveness when the device is not part of a cluster. Therefore, it’s necessary to enforce strict dummy device clustering rules to ensure proper performance of active P-type FinFETs.
Figure 2: TCAD simulated stress profile of a lonely P FinFET
and sense amplifiers, mismatches are intolerable. For a 6T-SRAM, with horizontal misalignment one pair of devices results in a reduced L (fast but very leaky), while the other pair results in a wider L (weak devices). Similarly, for vertical misalignment the mismatch is in W of the devices. The bottom line: you run the risk of having non-functional silicon. To alleviate this problem the scheme of digitizing the contiguous gate layer and
then using a cut mask to ensure proper printability is used. Clearly this approach results in the most satisfactory printout for devices. Also, it’s noteworthy that this approach of using a “cut mask” is not a FinFET-specific technique and applies to the formation of devices for planar as well as FinFET beyond 20 nm. FinFET design has a disproportionate number of RDRs. Lithography is only one reason for these RDRs: the fin patterning/formation process with the high
FinFET ageing Ageing is related to the physics of the high-K dielectric gate stack and is by no means a FinFET phenomenon, yet FinFET designers have to deal with this reliability concern in the form of simulating and accounting for the effects of negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) aging that alters the behaviour of the device. The industry’s experience (history) in this area is unfortunately limited and it’s an added variable to deal with.
NBTI, which impacts P-type devices and PBTI, which impacts N-type devices, are a shift (deterioration) in the threshold of the device, Vt, that is a function of Vgs, temperature, and time. It’s a partially reversible process that depends on the time a device is on and the corresponding duration of recovery (device off). It’s highly sensitive to high temperature. Over years of use a device threshold could shift significantly impacting the delay of a critical
path by as much as 7 to 10 percent. NBTI is much more critical than PBTI and NBTI is an order of magnitude higher than PBTI.
Soft error rate Soft Error Rate (SER) upsets caused by impinging particles are an important parameter to monitor, especially for SRAMs. How does SER look as we move from planar to FinFETs? The answer is simply: better.
Simply explained, charge generation caused by energetic impinging particles is in the substrate. In planar, a lot of it can reach the drain of the device and collect there, causing enough current to upset the storage node. In FinFETs, the conduction is mainly in the channel and, thus, most of the charge dissipates in the substrate and will not collect at the drain, making the probability of upset much lower.
Summary and conclusions FinFET device technology is the most promising technology for extending Moore’s law all the way to 7 nm. It offers excellent solutions to the problems of sub- threshold leakage, poor short-channel electrostatic behaviour, and high device parameters variability that plague planar CMOS. Furthermore, its ability to operate at lower supply voltage has extended voltage scaling, which had been levelling off, and allows further static and dynamic power savings.
Synopsys |
www.synopsys.com
Jamil Kawa is R&D Group Director at Synopsys
www.cieonline.co.uk
Components in Electronics
April 2013 19
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