MCUs & MPUs
The use of FinFETs in IP design
Jamil Kawa discusses the design opportunities and challenges stemming from the introduction of the FinFET device and links them to the manufacturing and reliability challenges and complexities associated with further scaling
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ecent announcements of FinFET roadmaps have accelerated the discussion about the opportunities and challenges associated with the use of FinFETs in IP design. It has also opened up the discussion about the future of CMOS scaling all the way down to 7 nanometers (nms).
FinFET technology has helped to alleviate several important challenges associated with continued scaling of planar bulk CMOS, but other challenges related to lithography such as tolerances associated with double-patterning mask alignment, as well as reliability and performance concerns associated with aging, continued to get more acute with every scaling step. What are the design opportunities and challenges that stem from the introduction of the FinFET device and how do we then link them to the manufacturing and reliability challenges that are associated with further scaling?
Device of choice
Due to its many superior attributes, especially in the areas of performance, leakage power, intra-die variability, low- voltage operation (translates to lower dynamic power), and significantly lower retention voltage for SRAMs, FinFETs are replacing planar CMOS as the device of choice.
In a planar FET a single gate controls the conductive channel. Such a gate does not have good electrostatic field control away from the surface of the channel next to the gate, resulting in leakage currents between source and drain even when the gate is off. By contrast, in a FinFET the transistor channel is a thin vertical fin with the gate
18 April 2013
fully “wrapped” around the channel formed between the source and the drain. The gate of the FinFET can be thought of as a “multiple” gate surrounding the thin channel. Such a multiple gate can fully deplete the channel of carriers. This results in much better electrostatic control of the channel and thus better electrical characteristics. The most relevant geometric parameters of a FinFET are its height H, its width (body thickness) Tsi, and its channel length L. The electrical width of a FinFET is twice the height plus the width.
At any one technology node FinFETs have several advantages over planar FETs, including mainly: • Good electrostatic control of the channel, meaning the channel can be “choked off” more easily. FinFETs boast a near-ideal sub-threshold behaviour (associated with leakage), something that’s not easy to achieve in planar technology without considerable effort. • Greatly reduced short channel effects. The short channel effects in planar technology are complex and have a significant impact on gate length variations and, therefore, on electrical performance. • High integration density, thanks to vertical channel orientation, delivers more performance per linear W than planar even after the isolation dead-area between the fins is taken into account. • Smaller variability, especially variability
resulting from random dopant fluctuation primarily due to doping-free or low doping channels.
An opportunity for IP design Design metrics of performance, power, area, cost, and time-to-market have not
Components in Electronics Figure 1: Planar FET vs. FinFET
changed since the inception of the IC industry.
Designing in FinFET broadens the design
window. Operating voltage continues to scale down, significantly reducing dynamic and static power. Additionally, short channel effects are significantly reduced, decreasing the guard-banding needed to deal with variability, and performance continues to improve (compared to planar at an identical node).
For memory designers, an added advantage of FinFETs is the significantly lower retention voltage of FinFET-based SRAM compared to that of planar.
The challenges
The FinFET is a significantly more complex device to model. Accurate FinFET parasitic extraction is more complicated. Generating good, yet compact, SPICE models is also more challenging than for planar devices. For most design activities the aforementioned complexities are transparent to the designer. FinFETs have a lower DIBL/SS (sub-
threshold swing) that is a desirable characteristic as far as leakage is concerned. On the other hand, the undoped (or very lightly doped) and practically fully-depleted channel renders the use of body biasing techniques commonly used in planar less effective, making alternatives necessary.
The finite granularity of the fin width W and the limited range of freedom in channel length for a given architecture make optimising analogue as well as digital design more complex. Granted that many fins can be “ganged” together to generate a desired W, still L and W are not exactly free continuous parameters. Also, FinFETs have a significant number of restricted design rules (RDR).
For SRAM design, optimising the ß ratio of a bit-cell is more difficult as W is quantized, and the flexibility in L as a tuning parameter is limited. Practically speaking, a ß of 1 or 2 are the two main choices available. That, in turn, creates the need for more advanced assist techniques to enhance SRAM yield.
Lithography and manufacturing Given the fact that EUV will not be ready for volume production any time soon, the use of double-patterning (DP) is a must for all layers with tight pitches. This is not unique to FinFET. In fact, it applies mostly to interconnect layers (BEOL), which are the same in planar and FinFET technologies.
At nodes below 22 nm, the concept of digitizing a whole active area and then using a “cut-mask” to generate the desired geometry is a direct result of mask alignment challenges associated with double-patterning. For circuits like SRAMs
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