This page contains a Flash digital edition of a book.
EMC & Circuit Protection


Either overvoltage or overcurrent events will start a current source, charging up the TMR pin. The charge current is related to the input to output voltage differential such that the timer period is shortened with increasingly severe faults, ensuring the MOSFET stays within its safe operating area. When VTMR reaches 1.25V the fault pin pulls low to indicate the detection of a fault. If the fault condition persists, when VTMR reaches 1.35V the MOSFET is turned off. The cool down period is set by pulling down the TMR pin with a 2µA current until it reaches a retry threshold at 0.5V and the MOSFET is turned back on. Figure 2a shows a typical application


Figure 1: Simplified block diagram of the LT4356


processors has set the trend toward POL (point-of-load) power architectures. The use of exotic, large, modular, bolt- down isolated regulators with multiple outputs supplying the final voltage rails at board level is giving way to distributed and highly efficient POL switching regulators. These are typically powered by an isolated intermediate supply bus within the LRU which in turn is fed with 28 volts DC or more, from the aircraft or vehicle power system.


One consequence of the shift to POL power architectures is the opportunity to re-distribute the surge protection from a central supply board to the individual circuit boards within an LRU. The lower load allows for a small and efficient solution


using a dedicated overvoltage protection IC.


Linear’s LT4356 surge stopper protects


loads from high-voltage transients and overcurrent faults. Figure 1 shows a simplified internal block diagram of the device. Under normal operation an external N-channel MOSFET is driven fully on and acts as a pass device. If the input voltage rises above the regulation point set by a resistor divider at the FB pin, the MOSFET becomes a linear regulator allowing the load circuit to continue to operate through the transient event. During an overcurrent event, the current limit loop controls the gate voltage on the MOSFET to limit the sense voltage across the Vcc and SNS pins to 50mV.


circuit with 12V input and in Figure 2b a 16V clamp level protecting a downstream DC-DC converter from 80V input surges. The LT4356 can operate over an input voltage range of 4V to 80V (100V absolute maximum) and can also be pulled below ground potential by up to 60V without damage. The addition of a small transient voltage suppressor can provide increased levels of protection from short high voltage spikes where required. The LT4356MP (Military Plastic) grade


product is guaranteed and tested for operation over -55°C to +125°C and is available in MSOP-10 or SO-16 packaging. All MP products also undergo enhanced screening, reliability monitoring and tighter in-process controls. The MP grade is offered with a lifetime warranty and products are available in lead-free or tin- lead terminal finishes. The use of robust protection circuits in LRUs is essential to meet the reliability requirements of military and aircraft equipment. The wide range of standards


Figures 2a and 2b: Application circuit


and specifications, equipment trends and moves toward POL power architectures have led to the need for small and efficient protection schemes that can be distributed around the boards in an LRU. Such circuits have traditionally been built from discrete components and are difficult and time consuming to optimise. The LT4356 surge stopper can form the basis of an effective overvoltage, overcurrent protection circuit.


Linear Technology | www.linear.com


Steve Munns, Product Marketing, Linear Technology Corporation


www.cieonline.co.uk


Components in Electronics


September 2011 21


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44  |  Page 45  |  Page 46  |  Page 47  |  Page 48  |  Page 49  |  Page 50  |  Page 51  |  Page 52