Mil Tech Trends: Controlling the UAV overhead (Part 1 of 2)
through the PCIe switch, one point is always CPU memory and the other point is always a PCIe device. Truly usable scaling requires distributed memory and a switched network with nonblocking, “many-to-many” connectivity to or from any module on the switch.
A modular hardware system that scales well is only a good start. Software tools must provide the programmer with intuitive or automatic access to the dense computational efficiency in the recon- figurable system. UAV payload devel- opment and deployment are impacted if a programmer has to drill down into a system’s architecture to find and devel- op solutions to meet an application’s performance requirements. There are standard computer languages available for programming the CPU and FPGA in a reconfigurable system, but simply using C or FORTRAN alone will not achieve ISR application performance requirements. C and FORTRAN are serial programming languages tradition- ally used for CPUs, where instructions
are executed serially, one instruction at a time. Performance in a reconfigurable system is achieved by parallel program- ming: multiple streams of program instructions acting upon multiple streams of data at the same time.
Fortunately, the scientific supercomput- ing community has already developed parallelization techniques for C and FORTRAN, many of which have been adopted by some reconfigurable system compilers. One method of programmati- cally specifying parallelism is the OpenMP parallel section pragma statement. On a traditional large cluster of microprocessors, the code blocks enclosed by the parallel section pragma may be executed in parallel on the CPUs. On reconfigurable systems, the code blocks specified by OpenMP-style pragmas are instantiated in the FPGAs so that these “hardware code blocks” execute in parallel. Another method is data streaming, where a series of calculations is overlapped in time; for example, a computational block may start executing when the first results of
computer languages available for programming the CPU and FPGA in a reconfigurable system, but simply using C or
“
FORTRAN alone will not achieve ISR application performance requirements.
the previous block are received instead of waiting for all results from the previous computational block to be produced before starting.
”
Along with parallelization techniques borrowed from scientific supercomputing, most reconfigurable system compilers perform automatic loop pipelining for execution performance. In addition, reconfigurable system compilers auto- matically create in FPGA hardware all
There are standard
36 March/April 2011 MILITARY EMBEDDED SYSTEMS
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