an FPGA. The reconfigurable system’s performance per watt is 1.7 times better than the CPU-only system, and 2.5 times better than the CPU/GPGPU system. Note the total power consumption for the CPU/FPGA combination is the lowest power consumption.
A major factor in rapid UAV payload deployment is the availability of stan- dard programming tools that are closely coupled with the reconfigurable com- puter hardware. The piecemeal method of integrating compilers, software tools, FPGA boards, and CPU boards from dif- ferent vendors slows down deployment. If the tools and hardware have different suppliers, a system runtime environment must be created to unify the system before meaningful application work may begin.
Once real application development finally begins, one vendor’s compiler macro libraries (assuming they do have libraries) will not be optimized for another vendor’s FPGA boards, and so the application development must either experience a reduction in the perfor- mance specification or a schedule exten- sion. These and other inherent difficulties in the piecemeal method of UAV payload
development conspire to decouple the word “rapid” from “deployment,” usually in an unanticipated manner, and always during application development. Thus, a complete, well-integrated software and hardware package from one sup- plier is typically the best route for rapidly deploying a UAV payload.
Scalable systems and parallel programming A modular, scalable system lends itself well to code reuse, which also accelerates deployment for UAV payloads. Modularity in software design allows proven code to
be reused across several ISR applications, while hardware modularity supports easy scaling of an ISR application according to mission parameters and a UAV airframe’s SWaP requirements. Most heterogeneous systems today use one form or another of PCIe to give coprocessors access to system memory through the CPU. How- ever, the effective scalability of PCIe is limited by its blocking “many-to-one” architecture (Figure 1). PCIe coprocessors access data and communicate with each other only through system memory on the other side of the CPU. While PCIe does provide point-to-point connectivity
Memory CPU PCIe x16
PCIe x16 PCIe x16 PCIe x16 PCIe x16
Figure 1 | Typical PCIe-based coprocessor architecture with limited scalability because of its blocking “many-to-one” point-to-point architecture
MILITARY EMBEDDED SYSTEMS March/April 2011 35
PCIe Switch
PCIe Coprocessors i.e., FPGAs, GPGPUs
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