Mil Tech Trends: Controlling the UAV overhead (Part 1 of 2)
dynamic partial reconfiguration, the FPGA does not have to be big enough to hold all of the processing algorithms. It only needs to be big enough to simultaneously hold the single largest data-processing algorithm, the main control algorithm, and the SCC implementation.
ACCI utilized unique dynamic partial reconfiguration to add to the capabilities of the UAV control and communication system, and to minimize the SWaP-C burden of doing so. The system has a proprietary Hardware Operating System (HardwareOS) that is static in the FPGA. HardwareOS provides system resource allocation and system services functions that an OS would provide in a traditional software based system architecture.
The UAV system relies on a library of application or algorithm accelerators developed by ACCI. The TUC-enabled algorithmic accelerators enable, besides security functions, on-UAV, real- time manipulation of telemetry and video data streams and data transcoding functions. For example, if the UAV is in a banked turn, the video frame is horizontally distorted by both the pitch and roll angles of both the UAV frame and the camera pan and tilt settings. This problem was solved by dynamically loading and running an algorithm to “counter-rotate” video frames in real time into the proper orientation.
The TUC system also transcodes the digital video from RS-170 format to MPEG-2 and H.264 formats, among others.
The system then combines the transcoded video with the telemetry from the autopilot, and other onboard sensors, into an MPEG transport stream that correctly emulates a Predator data download format. This allows the UAV data to be utilized by any system that currently handles Predator formatted data streams. And all of the data streams are encrypted for ground transmission.
The system can load every data packet transmitted to the UAV or every packet of captured telemetry or video data into static Block RAM (BRAM) on the FPGA, and then dynamically apply any desired sequence of algorithms to each packet as required. With TUC hardware acceleration, the entire frame processing of video stabilization, horizontal correction, Predator format transcoding, transport stream packaging, and encryption is done in less than 12 milliseconds. At 30 frames per second from the camera, 33 milliseconds are available between frames, thus allowing ample processing resources for future planned enhancements, such as automated target tracking and direct autopilot control.
A closer look: Dynamic partial reconfiguration While using SCC flow to help maintain Type 1 requirements, the real advantage of using dynamic partial reconfiguration is apparent: The system can reconfigure the FPGA more than 100,000 times per second. Moreover, the data flow and parallel processing inherent in the FPGA fabric minimize latency and
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30 March/April 2011 MILITARY EMBEDDED SYSTEMS
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