Mil Tech Trends: Controlling the UAV overhead (Part 1 of 2)


Rapid deployment of scalable, dense ISR payloads for UAVs


By David Pointer


In light of increasing demands for advanced rapid prototyping and deployment of ISR applications on UAV platforms, systems engineers would be wise to examine reconfigurable architectures and flexible software tools that match the job’s qualifications.


Reconfigurable computing systems are an excellent and increasingly popular choice to provide heterogeneous Digital Signal Processing (DSP) compute solu- tions for Intelligence, Surveillance, and Reconnaissance (ISR) applications on Unmanned Aerial Vehicles (UAVs). Reconfigurable systems can be created with lower Size, Weight, and Power (SWaP) and higher computational density for an ISR unmanned airframe applica- tion compared to other types of systems.


In addition, programming environments are now available using ANSI standard C or FORTRAN, and enable a program- mer to extract all possible compute per- formance from the hardware. The use of standard programming languages greatly reduces the learning curve, enabling much quicker application deployment when compared to programming environments that utilize a proprietary non-standard language or purely hardware languages. Thus, UAV ISR systems developers should consider reconfigurable computing


architectures and flexible software tools imperative in their designs.


Reconfigurable computing for UAV payloads


When considering rapid deployment of UAV payloads, reconfigurable hardware is key. At the core of a reconfigurable sys- tem is the FPGA integrated circuit. This device may be explicitly programmed to execute application-specific algorithms, and yields very high computational efficiencies relative to a general-purpose


2 CPUs Matrix multiplier


Floating-point precision Sustained GFLOPS Power (watts)


GFLOPS per watt


2 quad-core CPUs


Single 140


~150 0.9


device such as a CPU or a General Purpose Graphics Processor Unit (GPGPU). This computational efficiency, in turn, gen- erates high performance per watt for applications executing on reconfigurable systems, which then enables the creation of computationally dense/low SWaP designs for UAV-based ISR applications.


Table 1 compares the execution of a single precision, matrix multiplication bench- mark on a CPU-only system, a CPU paired with a GPGPU, and a CPU paired with


CPU+GPGPU


CPU+NVIDIA Tesla S870


Single 140


~245 0.6


CPU+FPGA


CPU+XD2000i+ EP3S260


Single 157


~110 1.5


Table 1 | Matrix multiplication performance/power ratio. Source: Altera Corporation, “FPGA Coprocessing Evolution: Sustained Performance Approaches Peak Performance,” WP-01031-1.1, June 2009 version 1.1.


34 March/April 2011 MILITARY EMBEDDED SYSTEMS


U.S. Navy photo by Mass Communication Specialist 1st Class Chris Fahey


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