CIE SEPT09 P31:Layout 1 07/09/2009 12:00 Page 31
EDA & Development
The next leap forward
manual layout without sacrificing
design style or quality.
At the heart of this productivity leap
is advanced device generation
technology that provides a more
flexible and dynamic way of
generating an optimized device layout
According to Rich Morse controllable automation promises to take schematic driven layout
(Figure 1). Because it eliminates the
need for time-consuming PCell
far beyond drag-and-drop device generation
scripting for the most common PCells,
faster layouts can be realised with less
effort.
A
ccording to Moore’s Law, the
With device generation technology,
number of transistors that can
parameterised devices are used in place
be placed on an integrated
of PCells. The devices retain the
circuit (IC) increases exponentially,
benefits associated with PCells, but
doubling approximately every two
they are independent of the foundry,
years. While the semiconductor
process or technology being used.
industry has taken full advantage of
They are categorised according to type
this scaling, steadily increasing the
(e.g., resistors, capacitors, transistors,
number of components per chip, more
Figure 1. Creating optimised layouts with less effort and in less time is now possible through
guard rings, and contacts/vias) and are
components translate into greater
the use of advanced device generation technology
readable as layout data in GDSII by
design complexity and an increase in
EDA tools.
the amount of time required to
were introduced to catch formats but also using an industry-
A key benefit of using device
complete a design. One area where
connectivity/wiring errors (LVS) and standard format like Tcl, describe what
generation technology is that it
this added complexity proves
manufacturing rule violations (DRC). the layout tool should do when an
enables a more automated and fully
especially problematic is layout.
A big leap in productivity was instance of the cell is used in the
controllable SDL flow. The control
Problems arise not only because more
realised with the introduction of SDL, design. The parameters quantify the
comes from intuitive, user-friendly
components must be laid out, but
a technology that allows designers to dimensions for the variables specified
device planning, wiring and
because the circuit and layout
automatically create a physical layout in a given instance.
manipulation capabilities like
designers are often two different
from a logic schematic. In a SDL flow, When PCells are placed using a SDL
symbolic device optimisation and
people, making communication of
users simply select components in the methodology, a layout is automatically
device matching. With symbolic
device attributes difficult.
schematic and “drag” them into the generated that reflects the parameter
device optimisation, designers are free
Automation technologies like
layout editor which then values and connectivity specified by
to optimise the device floorplan at a
schematic-driven layout (SDL) offer
automatically creates the physical the circuit designer in the schematic.
symbolic level without having to
one way of addressing this complexity,
design. Because the circuit designer does not
worry about parameters, design rules
while also improving productivity.Yet,
Today, analogue and custom digital have to enter any additional
or connectivity (Figure 2). Following
automation without control often
IC designers create schematics using information or assign connectivity an
completion of the floorplan and
forces designers to face undesirable
symbols that correspond to specific enormous amount of time is saved -
design optimisation, a device layout is
tradeoffs between setup time and
devices. They assign values for a time that normally would have been
automatically generated that matches
layout speed. With next-generation
variety of parameters prior to layout spent manually laying out the design.
the floorplan. The layout retains the
custom chips promising to be bigger
based on the results of simulations run Time savings also comes from the
connectivity and sizing defined in the
and even more complex, the time for
using foundry provided models. In the PCell “remembering” how it was
schematic.
another leap forward in productivity
case of custom layout design, flexible connected in the schematic, thereby
This same technology can be
has come. That leap - controllable
configurations are required to create a helping the designer with both
applied to resistor and capacitor
automation enabled by flexible device
design with optimal performance and automatic and manual routing.
layout. It can also be used to accelerate
generation technology - promises to
the densest possible layout.
more complex layout problems like
take SDL far beyond mere drag-and-
Consequently, designers typically Next big leap
matching devices. Using a controllable
drop device generation. Not only does
require a large variety of device sizes, There is little denying the benefits
SDL flow, critical layout planning
it place more control of the
meaning that hundreds or even brought to bear by SDL and PCells, but
issues can be addressed at a symbolic
automation in the hands of the
thousands of different device versions the layout automation they enable
level and design-rule correct layout
designer, but it also enables a range of
would be required to create a useful comes at a price. Designers using
automatically generated.
capabilities to aid designers in realising
and automated SDL flow. The conventional SDL flows are often
A pattern duplication capability
superior layout results in less time and
introduction of the parameterized cell forced to trade off the time and effort
adds even more automation to the
with less effort.
(PCell) brought an answer to this required to set up and use PCells,
SDL flow, enabling efficient layout of
dilemma. against a desire to speed layout results.
repeated circuitry patterns. Repeated
Road to automation
PCells are software “scripts” or Controllable automation offers a
patterns can also be optimised to
To better understand where the
sequences of commands used to define viable means of scaling SDL flows for
create a more compact layout using a
industry is headed with automation, it
physical layout based on a prescribed next-generation custom chips. Using
technique called pattern reuse.
is necessary to first look back at where
set of parameters. A single PCell takes it, designers gain the ability to control
To deal with growing circuit size and
it has been. In the early years of
the place of many fixed cells by not only how often and how much
design complexity, the layout process
semiconductor development, IC
allowing the substitution of different automation is applied, but the overall
has been forced to become much more
designs were tediously hand drawn on
values for specified dimensional process as well. Moreover, it is simple
automated, increasing productivity
mylar graph paper and manually
variables or parameters. The scripts, and intuitive to implement, enabling
with every technological advance. SDL
transferred to photomasks. As
written primarily in proprietary layout results that rival even the best
and PCells represent a significant step
computer performance improved,
forward in design productivity, but
hand-drawn circuits were captured
next-generation custom chips will
in crude Computer-Aided Design
undoubtedly demand a further
(CAD) systems. Polygon layout
evolution - namely, to controllable
editors came next and enabled
automation and advanced device
designers to work directly on the
generation technology. The
computer. Schematic editors
implementation of such
followed, allowing designers to draw
advancements is key to scaling
circuit designs graphically on
today’s SDL flow and creating
workstations. But communicating
superior layouts with less effort, in
design intent from the circuit
less time, and without sacrificing
designer to the layout designer
layout density or design style.
remained difficult, and required
laborious review of the schematic
SpringSoft | www.springsoft.com
and detailed, manual transfer of
Rich Morse is Technical Marketing
device attributes to layout. Layout
and EDA Alliances Manager for
vs. Schematic (LVS) and Design Rule Figure 2. More automated techniques allow on-the-fly device generation and optimisation
Laker Custom IC Design Solutions,
Check (DRC) computer programs with devices being easily swapped, merged, moved, split, and aligned at a symbolic level
SpringSoft
www.cieonline.co.uk Components in Electronics September 2009 31
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