CIE-SEP09-PG14-15:Layout 1 09/09/2009 09:48 Page 15
Automotive Electronics
Figure 2: A single FPGA can be used to provide post processing for a CMOS image
sensor and the interface for a high speed data link, reducing the size and cost of the
camera module
video output of the camera, as well downstream and 62.5Mbit/s back to
as overlaying information such as the module. A separate transceiver is
warnings on the camera video. All of needed to implement the physical
this is handled in a single FPGA LVDS (low voltage differential swing)
without the use of complex protocol, but this is an inexpensive
embedded processing or an component. Using this differential
embedded processor elsewhere in the approach also helps to reduce the
vehicle, thanks to the embedded susceptibility of the signal to EMI
digital signal processing blocks in and provides more electrical
the FPGA fabric. isolation, increasing reliability. Using
The embedded processing in the two copper wires dramatically
FPGA also corrects for any shading reduces the cost, weight and
of the lens and includes a de-mosaic complexity of the wiring harness,
resize aperture control that which is a major factor in the design
reconstructs a full colour, high of automotive electronics. Figure 2
resolution image from the camera, shows how the overall system could
again reducing the cost and be configured.
complexity of the camera module. Automotive system designers want
Local image processing also allows the flexibility to put camera modules
the host controller to focus on the in a wide variety of locations in the
display and human interface issues vehicle for a wide range of
to add more intelligence and ease of applications. It is increasingly
use to the system. important to implement more post
processing in the camera module
Interfaces and also to provide a cost effective
There are several available interfaces high speed interface for the video
for the camera modules, from the back to the user with minimal
automotive-specific MOST optical impact on the size and cost of the
networking to automotive versions camera module.
of other networking technologies Integrating the camera control
such as Ethernet and Firewire. and image post-processing in a small
One technology that is emerging form factor, inexpensive module
as a leading contender is a two wire based on a single FPGA with a cost
serial LVDS protocol developed by effective high speed connection
Inova Semiconductor called the allows the delivery of high quality
Automotive Pixel Link (Apix). While video data to the user with minimal
the MOST protocol is a potential impact on the central processing
standard for moving video data module. Using a high speed
around the vehicle, as an optical differential protocol such as Apix,
network it can be complex and again with the protocol and MAC
costly to implement with optical interface integrated into the FPGA,
transceivers and fibre links, provides a cost effective high speed
especially with lots of distributed video link that is immune to EMI
modules. Ethernet is also moving and reduces the cost and weight of
into the vehicle with automotive the wiring harness.
versions, but this is not necessarily An 'instant on' FPGA qualified to
real time and deterministic as it uses the automotive temperature range
a fall back and re-try approach, with a small footprint and low
which means it can be complex to component count can integrate the
implement multiple modules on the key camera control and video post
network processing blocks and link those
The Apix serial LVDS interface, in blocks directly to a low cost, high
contrast, provides high speed speed interface. This dramatically
deterministic data transfers while simplifies the design and
keeping the cost and complexity of development challenges for the
the link to a minimum by using a system integrator and minimises
serial approach. The MAC layer for both the footprint and the end cost
Apix is available from Inova to of the solution.
integrate into the logic of the XP2
FPGA, reducing complexity and bill Lattice Semiconductor
of materials, and this handles the | www.latticesemi.com
conversion from an 8bit wide video Satwant Singh is Director of
bus to a two or four wire serial Marketing Non-Volatile FPGAs at
stream running at 1Gbit/s Lattice Semiconductor
www.cieonline.co.uk Components in Electronics September 2009 15
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