High-Performance Computing 2019-20

as acting as a common backbone of IP components for IO connection with the external environment, such as memories and interconnected or loosely coupled accelerators. Te EPI is also developing accelerator

technology in tandem with the general- purpose processor. Te Accelerator stream will develop and demonstrate fully European processor IPs based on the RISC-V Instruction Set Architecture, providing power efficient and high throughput accelerator tiles in the GPP chip. Using RISC-V allows EPI to leverage

open-source resources at hardware architecture and soſtware level, as well as ensuring independence from non-European patented computing technologies. Te EPAC-EPI accelerator building

block is a tile containing up to eight vector processors and specialised units. Te processors are coherent, sharing L2 cache banks through an NoC. Te processors will support RISC-V vector instructions, and will also control the specialised units dedicated to stencil and deep learning acceleration. Te vector and stencil capabilities will address HPC workloads, while the deep learning units will target AI applications. With this CP approach, EPI will

provide an environment that integrates

a Say ChEESEny computing tile. Te right balance of computing resources for application

matching will be defined through the ratio of the accelerator and general-purpose tiles. Tis gives the EPI and its partners the

opportunity to develop a wide range of processors based on a single architecture. By varying the tilesets it could be feasible to provide architectural specialisation at the chip level. Essentially providing different processors for different types of system, such as AI or HPC for example. Although this may be a long way into the development of the EPI platform, building this kind of flexible platform could be beneficial to future technological advances. In August, Calista Redmond, CEO of the

RISC-V Foundation, said: ‘In addition to focusing on solutions for the HPC market, the EPI project also targets the autonomous vehicles industry and the data centre and servers market. As processing demands for these applications are skyrocketing – for example, as cars become more autonomous and capable of real-time decision making – novel silicon approaches are required to power the next generation of smart devices and machines.’ ‘As part of the EPI project, the

accelerator stream is working to develop and demonstrate European processor IPs based on the RISC-V instruction set architecture

HPC Yearbook 19/20

(ISA). Te accelerator will be designed for high throughput and power efficiency within the general-purpose processor (GPP) chip. Using RISC-V enables the program to leverage open-source resources at [the] hardware architecture and soſtware level, as well as ensuring independence from non- European patented computing technologies,’ added Redmond. While the development of this technology

will take some time, the initiative has announced that the first processor will be in place by 2021. Tis gives the HPC community another Arm-based processor that is being developed specifically for HPC. Just as China has moved its own efforts into the development of homegrown processor technology, Europe also sees its future in developing technology and not relying as heavily on US vendors as it has in the past. Te increase in competition in the

processor market will be beneficial to all HPC users, as it will help to drive innovation and create a market place in HPC that provides choice for those looking to develop and build supercomputers. Te combination of low power solutions

based on Arm technology, coupled with accelerators, whether homegrown or developed in the US by companies such as Nvidia or Intel, will provide a highly scalable and functioning system for HPC users.n

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