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HPC Yearbook 19/20


High-Performance Computing 2019-20


in support of a common objective can contribute to making Europe a leader in a high-technology sector, bringing significant benefits to all European citizens and businesses. We are now looking to the EU’s next long-term budget and our Digital Europe Programme, through which we have proposed a significant amount of investment in deploying a world-class supercomputing and data infrastructure.’ Gabriel added: ‘Te European High


Performance Computing Joint Undertaking is a good example of how EU countries can co-operate to drive innovation and compete globally in these highly strategic technologies. I am convinced the new supercomputers these sites will host will boost Europe’s competitiveness in the digital area. We have demonstrated the strength of our European approach, which will bring concrete benefits to our citizens and help our SMEs.’


Homegrown technology


With initial funding in place and the co- operation of the European member states, the EC intends to develop its own computing hardware. Intel has held the lion’s share of the CPU market for HPC, while this may be changing in recent years, the other options available to HPC users are also based on US technologies, such as IBM or AMD. To help Europe compete, the EU decided


to develop its own processor for use in HPC. Funded as an off-shoot of the EuroHPC the European Processor Initiative (EPI) was funded and first announced in May 2018 and commenced operations in December 2018. Te project aims to deliver a high-


performance, low-power processor, implementing vector instructions and accelerator technology with high bandwidth memory access. Tis will be achieved through the


development of a complete soſtware stack and final integration of circuits, or ‘tape-out’, in an advanced semiconductor process node. Te project aims to provide a competitive chip that can effectively address the requirements of the HPC, AI, automotive and trusted IT infrastructure markets. As has been shown in recent years, to deliver sustained HPC performance requires a balanced architecture that can match processor speeds with memory bandwidth, and interconnect technologies that can help ship data to the relevant parts of the architecture. Te reliance on powerful CPU


technologies or increased clock speeds has long passed. Now HPC developers focus on much lower power processor technologies, which can be stacked together and, in


16


This initiative demonstrates how joint investment between the EU and its member states in support of a common objective can contribute to making Europe a leader in a high-technology sector, bringing significant benefits to citizens and businesses





some cases, accelerated in a heterogeneous architecture using GPUs. Now that European efforts are


synchronised under EuroHPC, it enables the co-operating partners to pool national resources. In order to spearhead these efforts, the EPI project was established as one of the cornerstones of this strategic plan – it has gathered 26 partners from 10 European countries to develop the processor and supporting IP and ensure that the key competence of high-end chip design remains in Europe. If they are successful, European scientists and industry users will be able to access this home-grown technology which provides high levels of energy-efficient computing performance.


Risky business


Te technology is based on Arm and RISC-V technology, with the first processor scheduled for 2021. EPI intends to share a set of common technologies across different application domains. Starting


from the selection of processor technology, a low-power design approach ranges from massive parallelism, specialised architecture, low-voltage operating point, and fine grain power management. Te combination of these concepts should give them the high performance, low power solution that they are aiming for. Te soſtware stack will be designed


to integrate and take advantage of these features to achieve high-energy efficiency and maximise performance across a wide range of layers, from low-level firmware, up to system soſtware and application run-times. Tis approach is being referred to by the EPI as the Common Platform (CP). Te CP is organised around a 2D-mesh


Network-on-Chip (NoC) connecting computing tiles based on high-performance general-purpose CPU core with built-in FPU acceleration and specialised application- accelerators with different acceleration levels. A common soſtware environment


between heterogeneous computing tiles will help to harmonise the system, as well


www.scientific-computing.com/hpc2019-20


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