Staying in frame Product focus: frame grabbers


A roundup of the latest frame grabber releases, including CoaXPress models


Matrox Imaging’s new Rapixo CXP is a multi-link CXP 2.0 frame grabber, based on the latest version of CoaXPress. Te Rapixo CXP supports data rates of up


Active Silicon has released the FireBird single CoaXPress low profile board. Maintaining all the features of a FireBird board, this latest arrival has been optimised for cost, so it has a wider appeal for a greater range of applications. It is ideal for use with the latest range of small, lower-priced single-link CoaXPress cameras. CoaXPress in this combination offers a more affordable solution, with all the advantages of higher bandwidths, real-time triggering, long cable lengths and the robustness and high reliability of a dedicated vision standard. Te low-profile design of the frame grabber


allows the board to be used in small 2U enclosures; a full-height bracket is also available for standard PC cases. It is a four-lane Gen2 PCI Express board and is fitted with a micro-BNC connector, the latest standard for CoaXPress, which also supports PoCXP. Comprehensive I/O is offered, including front panel I/O. DMA engine technology, ActiveDMA,


guarantees zero CPU intervention, high-speed and low-latency image data transfer. In addition, long cable lengths are supported – up to 40 metres at 6.25Gb/s and more than 100 metres at 3.125Gb/s. All Active Silicon FireBird frame grabbers are


GenICam compliant as standard, and the board is supported by ActiveSDK soſtware. www.activesilicon.com


Euresys has launched the Coaxlink Quad CXP- 12, a four-connection CoaXPress CXP-12 frame grabber, and the Coaxlink Octo. Successful applications include 3D AOI, flat panel display inspection, printing


to four times 12.5Gb/s, with a PCIe x8 host computer interface to match, as required in high-speed, high-resolution machine vision applications. Te doubled bandwidth per connection is ideal for the new generation of high resolution, high frame rate image sensors. Matrox Rapixo CXP boards also offer custom


onboard image processing using a FPGA. Tey can also host the licence for Matrox Imaging soſtware, avoiding the need for a separate hardware key. Rapixo CXP features up to four connections,


and simplifies integration with support for Power-over-CoaXPress (PoCXP) that combines power, command and data interfaces on one cable. www.matrox.com/imaging


inspection and in-vehicle video transfer. Te Coaxlink Quad CXP-12 has four


CoaXPress CXP-12 connections, offering 5,000MB/s camera bandwidth; while the Coaxlink Octo has eight CoaXPress CXP-6 connections. Te Octo can connect up to eight CoaXPress cameras to one card. Both frame grabbers support the PCle 3.0 Gen


3 x8 bus, with 6,700MB/s bandwidth. Tey give 20 digital I/O lines, extensive camera control functions, and the Memento Event Logging tool. www.euresys.com


Silicon Software has introduced two members to its MicroEnable 5 Marathon CXP family of frame grabbers: the ACX-SP and ACX-DP CoaXPress boards for high-speed applications. Te FPGA-based frame grabber series has


been developed for the Camera Link, Camera Link HS and CoaXPress cameras. Four CoaXPress boards are now part of the series: the A-Series, ACX-QP with four ports, ACX-DP with two ports, and ACX-SP with one port, as well as the programmable FPGA version VCX-QP (V-series). Te frame grabbers support colour (RGB and Bayer) and monochrome area, line scan and CIS cameras across different topologies


32 Imaging and Machine Vision Europe • August/September 2018


– single, dual and quad configurations – and up to 25GB/s incoming bandwidth. Te new ACX-SP and ACX-DP frame grabbers


consist of smaller versions, with one or two camera ports for single link and dual link CXP cameras. Tey offer similar feature sets as the quad-port frame grabber, with an equally high bandwidth of 6.25Gb/s data rate per single CXP-6 connection. Te four ports of the ACX/VCX-QP frame


grabbers can be connected to four different CoaXPress cameras at the same time, with a multitude of pixel formats and bit depths. Te VCX-QP version FPGA is graphically programmable, with Visual Applets using data flow models. Existing FGPA hardware code – created with VHDL or Verilog – can also be integrated using VisualApplets Expert. silicon.software


@imveurope www.imveurope.com


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