Feature: Programmable logic


PVT (process, voltage, temperature). Tese must be considered separately since they influence accuracy differently. Te first one impacts accuracy directly: if a receiver and a transmitter have different latency at startup, the IEEE 1588 mechanism will not detect it and any unbalancing will directly impact accuracy – even averaging will not help. Notice in Figure 2 that both measurement sets are biased. Te second and third effect, surprisingly, have no impact


on accuracy. In fact, the latency variations due environmental conditions (voltage, temperature, etc.) will apply to both receiver and transmitter and the IEEE 1588 mechanism will cancel them out. Tis, however, does not mean that the time transfer should occur only once aſter startup. If we calibrate only once, the change in latency, although symmetrical between RX and TX, will produce an error in the slave clock, which will then build up with the temperature/voltage driſt. Te countermeasure is to re- sync at a pace faster than the temperature/voltage change.


Versal methods Xilinx’s Versal transceivers offer alternative methods to measure and control latency, both at startup and during runtime, which fall into two categories: buffer bypass and FIFO latency measurement. Te first allows bypassing the FIFO in both RX and TX direction, setting up a sophisticated clocking scheme to handle the data domain crossing with no timing errors. It also has minimal latency, which, although it may not be relevant for synchronisation applications, is key for other industry fields, such as high-frequency trading (HFT), for example. While buffer bypass solves the problem by setting the


transceiver latency to a fixed value, another very interesting set of techniques focuses on measuring the latency itself. If the latency is known at any given point in time, it can be easily re-used to mathematically correct the value of ‘the time of the day’, or TOD. Tis method is very interesting in synchronisation applications, since it offers a natural upgrade path for all IPs (for example, Ethernet) with no relevant change in the clocking architecture of the IP itself. Precision is achieved in both approaches because the


platform uses a hard-coded analogue phase detector built in the transceiver and analogue phase interpolators, controlled by the user, who can step up or down the clock phases with picoseconds-long increments.


Versal accuracy Te typical source of inaccuracy is the startup-to-startup change in latency due to the random phase that dividers can have aſter reset. Versal allows to either measure or set the latency at startup. Tis initial calibration stage ensures all sources of inaccuracy in the transceiver are removed. Te variation of latency (symmetrical for RX and TX) that


occurs during runtime can be compensated by the precision time protocol (PTP) mechanism itself, which begs the question: what is the advantage of measuring latency over time? Tere are many cases where the change in latency is not


Figure 1: Precision and accuracy


Figure 2: Start up to start-up latency variation


symmetrical between RX and TX, for example in passive optical networks (PONs) in telecoms. In other cases, the RX and TX paths can be on different physical devices, for example in test equipment. Different devices might happen to be at different temperature, process and power supply, which would yield a different trend in latency over time between RX and TX, giving rise to inaccuracy. Te Versal ACAP is a game changer in transceiver latency


control and latency measurement: from the nanosecond level of typical fabric clocks to the picosecond level offered by hard-coded analogue phase interpolators. And, lastly, when referring to “synchronisation application”,


it’s worth noting that any application that uses the ability to transfer the TOD between network nodes falls into this category and is very user-specific. In the general case it requires processors with proprietary software, a compute logic and different interfaces. In many cases it even requires fast ADC or DACs and/or DSP engines. With Versal, system architects and designers will be able to


implement their own applications, with their own expertise, in a single device. It is the easiest and fastest way to bring ideas to life – the full application can run on one chip, accurately synchronised.


www.electronicsworld.co.uk October 2021 29


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