Column: JESD204 standard
Verification challenges in the JESD204B standard for high-speed data converters
By Frank Farrelly, Product Engineering Manager, Analog Devices, and Chris Loberg, Senior Technical Marketing Manager, Tektronix
Figure 1: Jitter map, including identification of bounded uncorrelated jitter T 14 October 2021
www.electronicsworld.co.uk
he world of data converters is evolving: as the bit depth and sample rate go up, getting data in and out of a system becomes increasingly difficult. A
decade or two ago, with sample rates for high-speed converters limited to 100MSPS, using TTL or CMOS parallel data buses was sufficient. For example, a 12-bit converter with 12 pins dedicated to data could be implemented with reasonable setup and hold times with respect to the clock. As speeds exceeded 100MSPS, setup
and hold times for single-ended signals could no longer be maintained. To boost speeds, high-speed converters moved to differential signalling, but at the cost of increased pin counts. For example, a 12-bit converter would need 24 pins dedicated to data. To address the pin-count issue, serial
data interfaces were adopted. A converter data interface with 6× serialisation now allows that same 12-bit converter to transfer the data with just two differential I/Os (only four pins). Fast forward to today, and converters are being developed using the JESD204B specification for the data interface. Te JEDEC
standards organisation has published two versions of the JESD204 high-speed serial digital interface specification: Te first (JESD204 2006), brought the advantages of SerDes-based high-speed serial interfaces to data converters with a 3.125Gbps maximum speed rating. Its revision in 2008 (JESD204A 2008) added important enhancements, including support for multiple data lanes and lane synchronisation. Te second version of the specification, JESD204B, was developed by an international JEDEC JC-16 task group (Project 150.01), to provide enhancements such as a higher maximum lane rate, support for deterministic latency through the interface, and support for harmonic frame clocking.
Lack of compliance test specification Unlike many other high-speed serial interface standards, JESD204B does not include an official compliance test specification. A test specification is doubly valuable because it lists the tests that must be performed to ensure compatibility, as well as the procedures for performing them. Having consistent procedures used by different
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