Column: JESD204 standard


manufacturers ensures a common understanding of the specification and eliminates differences in assumptions. However, all is not lost: the information


needed to develop a set of tests and procedures can be found in the JESD204B specification. It is leſt up to each chip manufacturer and system developer to pull together the information.


Physical layer testing Physical layer, or PHY, tests relate to the individual data-lane driver and receiver circuitry: i.e., the analogue tests of a link. Tey do not include digital functionality or procedural tests. Working toward the goal of developing


a thorough list of PHY tests, or at least a list of recommendations, SerDes PHY tests can be obtained from the OIF- CEI-02.0 specification, section 1.7. Te JESD204B specification closely follows those recommendations, but with some modifications. For example, JESD204B does not specify random jitter as a standalone test item, but includes it under total jitter. Also, JESD204B specifies JSPAT, JTSPAT and modified RPAT as recommended test patterns, whereas the OIF-CEI-02.0 specifies the PRBS31 pattern. Tere are additional PHY tests that


could be performed that are not listed in the OIF-CEI-02.0 or JESD204B specifications. Other SerDes compliance test specifications include other PHY tests such as intrapair skew (for a transmitter) and intrapair skew tolerance (for a receiver). However, additional PHY tests are not required to ensure JESD204B compatibility; the intention is to use them to gain insight as to why a particular PHY test has failed. Once the list of tests is set, limits for


those tests can be obtained from the JESD204B specification and there are three sets of them: LV-OIF-11G-SR, LV-OIF- 6G-SR and LV-OIF-SxI5. A particular JESD204B device may support more than one set of limits, in which case the component should be tested against all supported limit sets. One point of potential confusion with JESD204B PHY testing is jitter


Having consistent procedures used by different manufacturers ensures a common understanding of the specification


terminology, since JESD204B and OIF- CEI-02.0 use different terminology to that of the test equipment vendors. Te typical jitter map is shown in Figure 1. Test equipment makers base their terminology on the industry standard dual-Dirac jitter model. Tis difference in terminology is a point of potential problems in test procedures, as jitter is quite a tricky topic. Table 1 shows our translation of the jitter terminology (the JESD204B specification uses different terminology for jitter from that used by test equipment vendors). Another point of potential confusion


with JESD204B PHY testing is the eye diagram for data rates above 11.1Gbps. Te JESD204B specification states that for data rates above 11.1Gbps to use a normalised bit time of 11.1Gbps. So, if running at 12.5Gbps (with an 80ps bit period), it advises to use the bit period for 11.1Gbps


(90.9ps). Te issue is that eye diagrams can be built by starting either at the edge of the UI or from the UI centre, and the JESD204B does not clearly state which reference to use. If at the UI centre, then at 12.5Gbps the eye diagram is bigger than normal, making it harder for a transmitter to pass but easier for a receiver to work. If the reference point is the edge of the UI, then at 12.5Gbps the eye diagram is smaller than normal, making it easier for a transmitter to pass but harder for a receiver to work. Ultimately, until this question is resolved, it is recommended to test against each of the two diagram options to ensure compatibility.


Timing testing Coming up with a thorough list of timing tests for JESD204B is not an easy task. Tere are at least a dozen timing diagrams in the specification, and it’s not immediately apparent which ones apply to the transmitter, channel or receiver. Also, some are only applicable to a particular subclass (0, 1 or 2). An official compliance test specification


would be especially helpful here if it were to simply consolidate the timing specifications into a single table, removing confusion. One benefit for developers is that


specifying timing for a JESD204B component is easier than specification implies. For Subclass 0 and 2, only device clock-to-SYNC~ timing must be specified; for Subclass 1, it’s only device clock-to- SYSREF timing.


Table 1: Jitter terms translation www.electronicsworld.co.uk October 2021 15


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