Feature: Thermal management
Figure 1: A NAND Flash-based automotive storage device has to satisfy a wide variety of requirements whilst tolerating the special constraints of the automotive environment
• Accelerated environmental stress testing; • Accelerated lifetime simulation testing; • Packaging and assembly tests; • Die fabrication testing; • Electrical verification; • Defect screening; • Package integrity testing. Tis qualification process is exhaustive and proven to effectively
screen out potentially defective parts. Components that pass the tests and achieve AEC-Q100 qualification have demonstrated a remarkably high level of reliability and integrity in a demanding set of environmental and application conditions. One of the most difficult elements of AEC-Q100 qualification for
NAND Flash-based storage products to achieve is to pass the high- temperature and accelerated lifetime simulation tests. Storage systems must maintain reliable operation at continuous temperatures of up to 85°C for AEC-Q100 qualification to Grade 3, and up to 105°C for Grade 2. And the compact, chip-style packages in which the latest products are housed, have more constrained thermal pathways than in the larger enclosure of a typical free-standing SSD used as a computing accessory. To maintain reliable operation and data integrity in automotive
storage devices, Silicon Motion applies various unique technologies that draw on its long experience in NAND Flash memory control. An understanding of these technologies will help the automotive system designer evaluate NAND-Flash-based storage devices with confidence that they are robust and reliable enough for use in vehicles.
High temperature operation To see how technology can counter the effect of high temperatures on NAND Flash cells, it is important to understand the operation of these cells. In Flash memory, data bits are represented by stored charge (electrons) in cells. When NAND Flash technology was first introduced, memory arrays were made of single-level cell (SLC) elements. In SLC NAND, the cell stores one bit of data – 1 or 0. As technology advanced, NAND Flash chip manufacturers responded to demand for higher memory density by developing
Figure 2: Cell size per bit in today’s TLC NAND is smaller than in SLC and MLC
multi-level cell (MLC) technology that stores two bits per cell, and then triple-level cell (TLC) technology, with three bits per cell; see Figure 2. Tis means that the cell volume per bit has declined with each new generation of NAND Flash. NAND cell size also shrinks as semiconductor fabrication processes advance from older process nodes to the latest sub-10nm nodes. Te high memory density of today’s TLC NAND Flash devices
means that a storage device such as Silicon Motion’s FerriSSD can provide up to 480GB of data capacity in a surface-mount BGA package, with a footprint of just 20mm x 16mm. But, the small size of a TLC means that it wears out at a faster rate
than an SLC, a factor that the Flash controller embedded in a storage device must take into account. Every program/erase (P/E) cycle slightly degrades the oxide layer in the cells on which a P/E operation is performed. Smaller TLCs have a thinner oxide layer than the larger SLCs, so they degrade faster and can, on average, withstand fewer P/E cycles. Tis can be resolved with our proprietary NANDXtend technology in the Ferri series storage devices. NAND Flash cells over time also experience electron leakage. If too
much charge leaks from a cell, its data can no longer be successfully read. Data retention – the length of time data can be stored in a cell – declines as more P/E cycles are performed.
www.electronicsworld.co.uk November 2022 31
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