Feature: Embedded
The importance of functional verification
By Susan Mack, Senior Engineering Manager at Sondrel D
esigning the front end of a chip is generally considered more fun than its verification. And yet, chip verifica- tion is a crucial part of
the design process and can take up as much as 70% of the development time. Typically, after a design is created,
verification engineers test it thoroughly, which is where exciting and interesting challenges lie. Real life can create unusual scenarios for a chip, and a verification engineer’s job is to find ways to test each design to make sure it will perform correctly whatever the setup. And, as chips become larger
and more complex, it is vital to automate and reuse verification tools and methodologies for speed and completeness. This is particularly important as some chips can have mission-critical roles, as in autonomous cars for example, hence they must
22 May 2021
www.electronicsworld.co.uk
With horizontal reusability, instead of running a simulation test at a particular level that could take many days, emulation takes only a few hours
perform correctly at all times – a million-to-one event could be disastrous if the chip does not behave correctly. An interesting new area in
verification is blending C-based SoC integration verification with horizontal and vertical reusability mechanisms. These are created on C-based
verification flows and components on the IP level first, then the sub- system level and, finally, the entire SoC, which avoids creating use cases specifically for each level. Not only are test scenarios created for vertical reusability, the verification plans that detail them check and develop the coverage points required for reuse. The plan clearly indicates these points, which are incorporated in the verification of a particular level. This allows us to identify suitable tests quickly, which ensures correct component integration, saving time and reducing errors. With horizontal reusability,
instead of running a simulation test at a particular level that could take many days, emulation takes only a few hours. Test benches help the transition from simulation to emulation quickly and easily via the SCE-MI interface, massively saving time over many tests.
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