Feature: Embedded design
Figure 1: The Agile Analog platform technology for generating IP unique to each customer and application
begins. Still, a small portion of the circuit will consist of new circuit elements, which typically is the part that takes up most of the engineers’ time and eff ort to diff erentiate the design.
External IP When it comes to IP in the analogue domain, experience shows that re- using existing IP is rarely as eff ective and trouble-free as expected, partly because of the inherent diffi culty of re-use, and partly because there are some defi ciencies in the way the IP has been supplied. Re-using internal IP or procuring external IP is meant to help SoC
Analogue IP procurement for fast tape-out of chip designs
By Tim Ramsdale, CEO, Agile Analog
T
he semiconductor industry’s phrase “new design project” carries a rich set of connotations. It is commonly used to describe a development activity from the very beginning, rather than a re-design, cost-reduction tweak or any other modifi cation of an existing design.
T e reality, however, is that no new chip design ever starts with a
completely blank canvas. Every ASIC or system-on-chip (SoC) design is a process of assembling and connecting building blocks and circuit elements that already exist in the form of IP developed and re-used in- house or from a third party, before any notionally ‘new’ design project
20 May 2021
www.electronicsworld.co.uk
or ASIC development teams get faster to a successful tape-out through optimised design. Existing IP should ideally reduce development eff ort and eliminate failures, saving time and costs. When chip development begins, when evaluating third-party sources
of analogue IP specifying parts must be clear: say, a “12-bit ADC”, for instance. But, within this generic category there must be a set of specifi cations that govern its IP’s implementation in the design – for an ADC this will be parameters such as operating voltage, sampling rate, linearity, noise, conversion speed, and more. Also, this IP must fi t the fabrication and process node the development team has chosen. Hence, this set of specifi cations must always be unique, yet traditional third- party suppliers of analogue IP have not been providing it.
Analogue vs digital T e unfortunate mismatch between what customers want (analogue IP that is uniquely confi gured to match an application) and what the third- party analogue IP market supplies (standard, off -the-shelf product) has arisen because the analogue IP market has borrowed its business model from the digital IP world, and what works for digital IP is not well suited to analogue IP. In digital electronics, functions can be specifi ed in a clear-cut way:
interfaces are standardised and confi gurability is available at RTL level, accessible to the user. T is means that digital IP suppliers can create standard IP products that perform standard functions, but with some confi gurability for the chip integrator guaranteeing that IP with same functionality. One user’s instance of 256-bit AES hash cryptography, for example, will be substantially the same as every other user’s instance. Moreover, digital IP can be synthesised to the target process by the chip integrator. T is means that digital IP suppliers can create a single instance of an IP product that is not only portable to many processes and nodes, but can be also easily optimised for speed, performance and power through the synthesis tools. Hence, digital IP suppliers can make a
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44
