Feature: Embedded design
Figure 2: A new set of capabilities underpins Agile Analog’s remodelling of the analogue IP supply chain
successful business out of creating a standard IP product to sell many times to many customers. Tis model does not work for analogue circuits because the
fundamental characteristics of analogue systems are different. In a sensor, for instance, the requirements for crucial parameters such as sensitivity, accuracy, precision, linearity or stability over temperature differ from application to application. In addition, optimising a single one of these results in trade-offs from others – meaning that the super- set solution tends to consume more power and occupy larger area than the application can allow. What’s more, the behaviour of analogue circuits varies substantially
from one fabrication process and node to another, even when made in the same foundry. So, whereas in the digital domain the cost of re- targeting is small thanks to digital synthesis, in the analogue world it is much higher – oſten approaching the cost of an original design. Tis, then, means that the conventional analogue IP supplier must choose to either provide standard, one-size-fits-all IP product or become a design services supplier. Tese are all unpalatable choices because, in the first instance, the customer fails to get IP that fits his specification, ending up with a sub-optimal design, and, secondly, they must rework the IP for each design. Ten, the economies of the IP market do not support a proper
design services model: full-custom IP design is very expensive and can take up to two years. Customers expect standard IP to be much cheaper than custom design, so the IP supplier takes shortcuts to minimise the time and effort in the rework of a “standard” IP product. Te result is the IP user receiving analogue IP that is not well verified, performs poorly and takes up precious internal development resources to optimise, which defeats the objective of buying in IP. Oſten, reworked versions of standard IP products are poorly supported by test data, qualification or documentation. All these issues have depressed the demand for analogue IP.
New approach Interestingly, the same problems are encountered in internally- developed analogue IP projects. What’s needed are robust, high- performance design automation tools to assemble new IP from basic analogue circuit building blocks. Agile Analog has created a new approach to analogue design automation, backed by artificial intelligence, helping generate new, custom-designed analogue IP blocks with a fraction of the effort required by conventional, manual, analogue circuit design.
Te newly-generated analogue IP is still customised, however: it
exactly matches the unique specifications set by the customer for the application and optimisation processes – speed, power consumption, die area and other parameters. Te IP is compiled according to the specifications of the foundry’s process development kit (PDK) for the fabrication process and node selected by the customer. Te process is entirely automated and typically takes fewer than 12 weeks from specification to provision of verifiable foundry-ready IP. Te customer can evaluate and test the IP’s quality through the extensive deliverables provided during the generation process; see Figure 1. At every step, from functional description to verification, to integration and testing, the customer receives detailed datasheets, simulations and test reports that fully document the performance and characteristics of the IP. Tis breakthrough has remodelled the analogue IP supply
chain; see Figure 2. Now, custom-configured IP can be generated in the time previously took to procure standard, off-the-shelf IP. Te Agile Analog platform is qualified to generate IP in various functional domains, including linear power regulation, temperature sensing, reference generation, tamper detection and data conversion. Te development roadmap will see continual expansion of the domains supported by the platform. The generated IP is compatible with almost any CMOS
process, and is currently running on a broad set of nodes, including FinFET processes down to 12nm. If the node, process or foundry change mid-design, the platform easily accommodates that by re-optimising and recompiling for the new process in matter of days.
Relying on commercial analogue IP With standard analogue IP products, customer engagement involves finding the standard product variant that is the closest match to the application’s requirements. In other words, a question of finding the least bad compromise. Agile Analog’s technology has enabled a new approach to
the procurement of analogue IP, one in which the specification process becomes more interactive. Tis means that, for the first time, commercial analogue IP can perform the functions it is supposed to, easily integrated into and optimised for chip designs and fabrication processes, in effect freeing the design team to focus on the unique, added-value functionality for which there is no third-party IP.
www.electronicsworld.co.uk May 2021 21
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