Column: JESD204 standard


Checking the SYNC~ signalling: lIf SYNC~ is static and logic low,


the link is not progressing beyond the CGS phase. There is either an issue with the data being sent, or the JESD204B receiver is not decoding the samples properly. Verify that the /K/ characters are being sent, as well as the receive configuration settings, the SYNC~ source and board circuitry, and consider overdriving the SYNC~ signal in an attempt to force the link into ILAS mode to isolate the link receiver vs. transceiver issues. Otherwise, consult the device manufacturer.


lIf SYNC~ is static and logic high, verify that the SYNC~ logic level is configured correctly in the source device. Check the pull-up and pull- down resistors.


lIf SYNC~ pulses high and returns to logic low state for less than six multiframe periods, the JESD204B link is progressing beyond the CGS phase but not beyond the ILAS phase. This would suggest that the /K/ characters are fine and the basic functions of the CDR are working. Proceed to the ILAS troubleshooting section.


lIf SYNC~ pulses high for more than six multiframe periods, the link is progressing beyond the ILAS phase and is malfunctioning in the data phase; see the data phase section for troubleshooting tips.


Checking serial data lVerify that the transceiver’s data rate


and the receiver’s expected rate are the same.


lMeasure the lanes with a high impedance probe (differential probe, if possible); if characters appear incorrect, make sure that the lane differential traces are matched, the return path on the PCB is not interrupted, and devices are properly soldered on the PCB. Unlike the (seemingly) random characters of the ILAS and data phase, CGS characters are easily recognisable on a scope (if a fast enough scope is available).


Finding out why it is not working requires a good understanding of likely scenarios


lVerify the /K/ characters with high- impedance probe. If the /K/ characters are correct, the


transceiver side of the link is working properly. If not correct, the transceiver device or board lanes have an issue.


lIf DC-coupled, verify that the transmitter and receiver common- mode voltage is within specification for the devices. Depending on the implementation,


the transmitter common-mode voltage can range from 490-1135mV. Also, the receiver common-mode voltage can range from 490-1300mV.


lVerify that the transmitter CML differential voltage on the data lanes (note that the CML differential voltage is calculated as two times the voltage swing of each leg of the signal). The transmitter CML differential


voltage can range from 0.5-1.0Vp-p for speeds to 3.125Gbps; 0.4-0.75Vp-p for speeds to 6.374Gbps; and 0.360- for speeds to 12.5Gbps.


0.770Vp-p


lVerify the receiver CML differential voltage on the data lanes (note that the CML differential voltage is calculated as two times the voltage swing of each leg of the signal). The receiver CML differential voltage for speeds for speeds for


can range from 0.175-1.0Vp-p to 3.125Gbps; 0.125-0.75Vp-p to 6.374Gbps; and 0.110-1.05Vp-p


speeds to 12.5Gbps.


lIf pre-emphasis is an option, enable and observe data signals along the data path.


lVerify that the M and L values match between the transmitter and receiver, otherwise data rates may not match. For example, M = 2 and L = 2 will expect half the data rate over the serial interface compared with M = 2 and L = 1.


lEnsure that the device clock going to the transmitter and receiver is phase- locked at the correct frequency.


2. Can’t get beyond the ILAS mode if SYNC pulses high for approximately four multiframes lLink parameter conflicts. Verify link parameters are not offset


by 1 (many parameters are specified as value -1). Verify that the ILAS multiframes


are transmitting properly, the link parameters on the transceiver device, the receiver device and those transmitted in the ILAS second multiframe. Calculate expected ILAS length (tframe , 4 × tmultiframe


tmultiframe ), verify ILAS is


attempted for approximately four multiframes.


lVerify that all lanes are functioning properly. Ensure there are no multilane/multilink conflicts.


3. You can get into the data phase but occasionally the link resets (returns to CGS and ILAS before returning to the data phase) lInvalid setup-and-hold time of periodic or gapped periodic SYSREF or SYNC~ signal.


lLink parameter conflicts. lCharacter replacement conflicts. lScrambling problem, if enabled. lLane data corruption, noise, or jitter could force the eye diagram to close.


lSpurious clocking or excessive jitter on the device clock.


4. Other general tips when troubleshooting links: lRun the converter and link at the slowest allowed speed, as this enables the use of lower-bandwidth measurement instruments that are more readily available.


lSet minimum allowed combinations of M, L, K, S.


lUse test modes when possible. l Use Subclass 0 for troubleshooting. l Disable scrambling while troubleshooting.


www.electronicsworld.co.uk May 2021 17


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