Feature: Medical


Figure 4: End-to-end data path protection eliminates bit errors caused by internal data transfers


Figure 5: 85o


C data retention simulation


NAND Flash memories is a particularly important source of bit errors – and one particularly diffi cult to reduce or eliminate.


Factors aff ecting data retention Laboratory testing of NAND Flash memory arrays has revealed two primary ageing factors in data retention:


1. Program/Erase (PE) cycling: T e process of writing a data bit to a memory cell and erasing it wears out the cell, reducing its capacity to hold charge. T e more P/E cycles the memory cell is subjected to, the shorter the cell’s data retention period will be.


2.High operating temperature: At higher temperatures, NAND Flash memory cells age faster, so the duration of data retention falls faster; see Figure 3. In addition, the two eff ects – P/E cycling and extreme temperature – also combine to reduce data retention even further. Data retention can drop to as little as two days at 85°C for a Multi-Level Cell (MLC) NAND device which has undergone its rated maximum number of P/E cycles.


Solving the data retention problem To deal with the data retention problem, the SSD industry turns to two methods: First, Error Correction Codes (ECC) for detecting and


www.electronicsworld.co.uk March 2024 17


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