Feature: Communications design Column: Going Green
controls on the multi-core processor. Te presence of both an FPGA and an MPU on the same chip,
It aims to show how DC microgrids can support the EU’s green ambitions and improve its technology readiness for a widespread use of microgrids
however, means that the system design team has to straddle two worlds – FPGA and microprocessor – and work in two independent design environments. Te PolarFire SoCs’ toolchains feed into a configurator which generates: • Te ‘soſtware’ configuration – the C data structures for initialising the memory map – which will be used in the SoſtConsole integrated development environment (IDE);
It aims to show how DC microgrids can support the EU’s green ambitions and improve its technology readiness for a widespread use of microgrids. Launched in September 2020, the project will set up two microgrids in Spain and France, using solar power, energy storage systems, V charging points and other DC loads. o achieve this, TIGON will rely on
• Te ‘hardware’ configuration – a so-called component – used in the Libero FPGA IDE. Te interaction between the two IDEs is shown in Figure 4. Design simulation is also supported by separate tools: Renode
(an open source soſtware development framework) for the soſtware running on the multi-core processor part, and ModelSim for the FPGA part of the SoC. Microchip has also made good provision for debugging the E complex applicatio s that will run on the PolarFire SoC. Its T on-chip-debugging mechanism communicates through a JTAG p interface to debug tools:
ioneering grid technologies including the latest energy-management systems, solid- state transformers and DC/DC converters. In all these projects, energy management
systems are just as important as the infrastructure they manage. If energy
• C code can be debugged using a traditional openOCD debugger;
• Te FPGA debug tool is more specialised, with a debug mechanism embedded by default in the component to give dynamic access to any internal node of the FPGA matrix.
companies are to take advantage of the flexibility and resilience offered by DC, the ability to analyse data in real time is essential – especially when DC networks are connected to renewable power.
A dedicated tool, Smartdebug, uses this internal debugging circuitry to provide an intuitive means to debug the FPGA-based part of the application. Interestingly, the conditions for porting an application to the RISC-V
environment are similar to those within the Arm environment. No two Arm core-based devices will have the same memory map and, equally, no two RISC-V-based systems will share the same memory map. So porting from one Arm core to another in principle requires the same effort as porting from an Arm core to a RISC-V core.
Essential parameters To meet government’s environmental targets, as well as rising energy demand, there is a real need for flexibility and controllability in the energy grid. As the growing number of DC projects shows, DC infrastructure offers one solution to futureproof the network and create a resilient, low-carbon grid.
Design-friendly development environment Te PolarFire SoC, then, offers the advantage of integrating in a single chip both programmable hardware capabilities and a high-performance, multi-core platform for soſtware applications. Tis hybrid architecture does entail the use of two development environments in parallel, but Microchip has taken great care to provide the user w gitrh a comprehensive set of tools that are extremely well integrated, and provide the capability for design teams to work productively in: • Creating or migrating the system;
If DC infrastructure is to be
widely used, its scaleability, security and connectivity become essential. Also essential is the ch ice of software platform, which should scale up with these needs and enable eater connectivity and remote
communication without compr mising security. Whether it is renewable power plants, energy storage systems or EV
• Simulating the design; charging points integrated into the grid, • Programming both the hardware resources in the FPGA portion of the chip, and app clication soſtware running on the processor cluster; and
• Debugging the system.
softwa e like COPA-DATA’s Zenon an make each asset more controllable and efficient – ideal for smart-grid applications.
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www.electronicsworld.com June 2022 09
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