Feature: Power Supplies
range and a certain output capacitance range, among other factors. Te Basic Linear Dropout Regulator (LDO) with an NMOS pass
element is shown below in Figure 1. In this setup, EA represents the error amplifier, R1, R2 are the feedback resistors, and the NMOS acts as the pass element. VDD is the supply voltage, Vref is the reference voltage for the LDO, and Vout is the output voltage.
Voltage regulation for power management
By Preethi Ashwath MS, Senior Analog Design Engineer, Analog Devices
Power supplies play a crucial role in any integrated circuit (IC) chip, which typically has a limited number of external power supplies.
voltage source, maintaining a constant output voltage despite variations in output current load. While every designer aims for an ideal design, analog circuit design has its own limitations. We can design a voltage regulator to remain within regulation for a specific output current load
A 34 June 2025
www.electronicsworld.co.uk
ll other voltage references are generated internally within the chip. While a bandgap reference provides a voltage that remains stable despite changes in temperature and variations in the power supply output load, a linear low-dropout voltage regulator is necessary to ensure ongoing stability.
Te main feature of a voltage regulator is to function like an ideal
Equation (1): Defines the minimum voltage difference needed between input and output for proper LDO regulation. Equation (2): Sets the LDO output voltage using a resistor divider and the reference voltage. Equation (3): Describes the feedback ratio used in the voltage divider network. Equation (4): Shows that when ?=1?=1, the output voltage equals the reference voltage. he LDO is configured as a unity-gain buffer, and the output voltage is equal to the internal reference voltage. Tis is typical in fixed-output LDOs where no external resistor divider is used.
Figure 1: NMOS based LDO Te dropout voltage depends on the topology of the NMOS and
PMOS pass elements. To reduce the dropout voltage in the design, a charge pump is added to maintain the gate voltage of the pass element without affecting the dropout. Additionally, the dropout voltage is influenced by the size of the pass element and the output current loading. A lower drop out voltage improves efficiency in low voltage Power Management IC(PMIC).
Equations for LDO
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