Column: Silicon systems design


can’t be linked back to a requirement, specification section, coverage item or sign-off criterion, it becomes difficult to defend its contribution to verification confidence. A lack of traceability is especially dangerous late in a project, when teams are under pressure to close regressions, approve waivers and make release decisions quickly. Te solution is not to avoid AI, but to


keep it inside a disciplined verification process.


Reusable intent models matter Structured verification methods already provide useful foundations for AI-assisted flows. Portable test and stimulus are relevant because they represent stimuli and scenarios in a form that can be reused across platforms such as simulation, emulation, FPGA prototyping and post- silicon validation. Tat matters because system behaviour increasingly must be verified across multiple execution environments. Intent should not be trapped in isolated directed tests. SystemVerilog also remains central


because it provides widely used mechanisms for assertions, coverage, constrained-random verification and testbench development. UVM (Universal Verification Methodology) adds further value by encouraging reusable components, layered environments and consistent testbench organisation. Tese methods provide the scaffolding needed to make AI output reviewable rather than ad hoc. AI can be valuable within this structure.


It may help draſt an assertion from a protocol rule, suggest coverage bins from a scenario list, summarise a failing regression, identify repeated error patterns or retrieve methodology guidance. But the generated output should still be mapped back to the verification plan and reviewed by an engineer. AI should help implement and analyse the strategy, but it should not silently redefine it.


From metrics to sign-off evidence Sign-off is not a single metric. It is a judgment that the remaining risk is


Verification intent is the engineering definition of what must be checked, why it matters, where it applies and what evidence is required for confidence


acceptable based on the available evidence. Tat evidence may include passing regressions, coverage closure, assertion status, formal results, bug trends, waiver reviews, scenario completion, emulation results and lessons from previous silicon. AI can help teams navigate this


evidence. It can identify patterns, summarise changes, correlate failures, highlight coverage gaps and reduce the time spent searching through large volumes of data. These are meaningful productivity gains. But evidence still requires


interpretation. A coverage gap may be irrelevant, or it may represent a serious missing scenario. A failing assertion may expose a design bug or reveal an invalid assumption. A waiver may be justified, or it may conceal residual risk. A summary may be useful, but it is not the evidence itself. For this reason, AI-assisted


verification needs clear review gates. Generated tests should be linked to verification objectives. Generated


14 July/August 2026 www.electronicsworld.co.uk


assertions should be checked for semantic correctness. Debug summaries should be validated against logs and waveforms. Coverage recommendations should be mapped to the plan. Waiver suggestions should be treated with particular care.


Human review remains central AI changes the work of verification engineers but it doesn’t remove their accountability. Engineers may spend less time on repetitive drafting, searching and summarising, and more time on reviewing intent, checking assumptions, validating generated content and making risk-based decisions. The need for review, traceability and


accountability is also why AI adoption in verification should be governed. Teams need rules for what AI may generate, what must be reviewed, what data may be used, how outputs are traced and how sign-off evidence is preserved. The NIST (National Institute of


Standards and Technology) AI Risk Management Framework is not a semiconductor verification standard, but its emphasis on risk management is relevant to any engineering environment where AI output may influence decisions. The guiding principle is simple: AI can


assist verification, but it must not weaken the verification argument.


Continued influence AI will continue to influence design verification. It can help engineers move faster, reduce friction and focus more time on judgment rather than repetitive work. But the central discipline of verification doesn’t change. Teams still must know what they are trying to prove, why it matters, what evidence is sufficient and what risk remains. Sign-off still depends on engineering


intent. AI can support the process, but confidence comes from the quality of the verification argument, the strength of the evidence and the judgment of the engineers responsible for the design.


This column continues in next month’s edition of Electronics World


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44