Feature: RF and microwave


Figure 5: Single-channel output (-26.17dBm)


Figure 4: Close-up of the RF absorption wall


application affects the system calibration in any way. See the results of this baselining in Figures 5-6.


PLL phase rotation calibration Phase rotation calibration was performed in three steps, each targeting a different PLL IC: Step 1: Rotate the first ADF4382 (Channels 1 and 5 active) in 5° increments from 0° to 360°, then refine in 1° steps to find the null. Step 2: Add Channel 9 and rotate the second ADF4382 similarly, relative to the already nulled first PLL pair. Step 3: Add Channel 13, and repeat the rotation of the third ADF4382 and null-finding relative to the first and second PLL pairs. See Figure 7 for the null finding result at this step.


Performance metrics Following the PLL phase rotation calibration and RF absorption wall installation, the Quad-Apollo MxFE platform demonstrated significant improvements in both output power and spectral purity. Tese metrics were evaluated across a range of operating frequencies to assess the robustness of the spur mitigation strategy. Te calibrated system showed a consistent increase in transmit


output power across all active channels. Tis improvement is attributed to reduced interference from clock spurs, which previously limited the effective dynamic range of the DAC outputs. Te enhanced power levels indicate that the signal path is now less contaminated by unwanted spectral components, allowing


Figure 6: Combined channel output post-calibration (with absorber applied, clock spur power ~ -55dBm)


Figure 7: Null-finding calibration result (monitoring clock spur magnitude at Step 3)


www.electronicsworld.co.uk April 2026 39


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